旨在测量处理器浮点性能的基准测试工具，
benchmark tools aimed at measuring floating point performance of processors, (2023-09-27, Fortran, 0KB, 下载0次)
Navier-Stokes方程解算器的当前CPU版本，
Current CPU version of our solver for the Navier-Stokes equations, (2023-07-06, Fortran, 0KB, 下载0次)
Labiew开发的上位机，有10路波形显示，能够作为智能车或者飞行器数据波形的绘制。
Labiew development PC, there are 10 road waveform display can be used as drawing smart car or aircraft data waveform. (2014-10-21, Fortran, 193KB, 下载1次)
第一，DDS模块是一个比较常用的用数字方式实现模拟信号的方法，以前一直只用了频率控制，这一次还通过深入理解用上了相位控制，从这个角度来讲，可以用FPGA小菜一碟的实现频率和相位可控的多通道SPWM波，然后再去外加上RC滤波电路和运放电路就可以实现可控正弦波。
第二，这里的DDS模块还有产生一个可逆计数器的计数使能时钟和方向控制时钟，需要具体说说的是，如果你输出的正弦值是8位的，那么你的计数器的计数范围是在0---255---0，如果你输出的正弦值是9位的，那么你的计数器的计数范围是在0---511---0。还有，每此计数变化后（一个“数字”三角波产生），DDS中只输出一个正弦值，进行比较。
First, the DDS module is a more commonly used in digital way to realize analog signal, the method of used in frequency control, this time also by deep understanding of using phase control, from this perspective, you can use the FPGA implementation of a piece of cake of frequency and phase controlled multichannel SPWM wave, and then to plus the RC filter circuit and the op-amp circuit can realize controllable sine wave.
Second, the DDS module and create a reversible counter count can make the clock and direction control clock, need specific about is that if you output sine value is 8 bits, so is the scope of your counter counts in 0-255-0, if your output sine value is nine, so is the scope of your counter counts in 0-511-0. Also, every change after the count (a "number" triangle wave), only in the DDS output a sine value, the comparison
(2013-12-20, Fortran, 159KB, 下载6次)
51单片机定时器计算工具 源代码
51单片机定时器计算工具
51单片机定时器计算工具
51 single timer calculation tools source code
51 single timer calculation tools
51 single timer calculation tools (2013-12-12, Fortran, 3KB, 下载1次)
PSCAD软件搭建SVC（静止无功补偿器）模型实例
PSCAD software to build SVC (Static Var Compensator) model instance (2011-06-28, Fortran, 14KB, 下载196次)