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[VHDL/FPGA/Verilog] fpga- 多数表决器

实现一个多数表决器输入分别是 a b c 输出是 f f= ab+bc+ac (有两个或者两个以上同意 f 的值为1)
Implementing a majority voter The input is a B C and the output is f, respectively. F = AB + BC + AC (two or more consent values of F are 1) (2019-04-16, Video, 990KB, 下载0次)

http://www.pudn.com/Download/item/id/1555382945340926.html

[VHDL/FPGA/Verilog] 06_lcd7_touch

基于7Z010的触摸屏驱动程序.开发板使用的是Xilinx公司的Zynq7000 系列的芯片，型号为XC7Z010-1CLG400C， 400 个引脚的 FBGA 封装。 ZYNQ7000 芯片可分成处理器系统部分 Processor System（PS）和可编程逻辑部分 Programmable Logic（PL）。在 AX7010 开发板上，ZYNQ7000 的 PS 部分和 PL 部分都搭载了丰富的外部接口和设备，方便用户的使用和功能验证。
Touch screen driver based on 7z010 (2017-04-20, Video, 62341KB, 下载16次)

http://www.pudn.com/Download/item/id/1492686786618805.html

[VHDL/FPGA/Verilog] CA-code

生成CA码verilog代码，quartusII开放环境，含源代码和仿真文件（波形、testbench）
CA generated code verilog code, quartusII open environment, including source code and simulation files (Waveform, testbench) (2014-05-09, Video, 3KB, 下载10次)

http://www.pudn.com/Download/item/id/2535924.html

[VHDL/FPGA/Verilog] PCB

这是我自己用altium designer 设计的电压比较器，由于分类和开发环境不懂选，就乱选啦，不好意思
This is my own design with altium designer voltage comparator, and development environments do not understand the classification election, election chaos friends, sorry (2013-08-20, Video, 8244KB, 下载12次)

http://www.pudn.com/Download/item/id/2335255.html

[VHDL/FPGA/Verilog] A-high-performance-channel-filter

这是一篇经典的设计文档，介绍了滤波器设计中的几个重要问题，值得设计滤波器的朋友们阅读。
This is a classic design documents, several important issues in the filter design, worthy of the design filter friends to read. (2013-04-28, Video, 1307KB, 下载2次)

http://www.pudn.com/Download/item/id/2220352.html

[VHDL/FPGA/Verilog] tvtest

１前言电视信号发生器是电视行业内必要的测试、维修工具。采用ＭＣＳ—５１单片机设计制作的电视信号发生器能产生八种最常用的Ｒ、Ｇ、Ｂ、ＳＹＮＧ测试信号。它与由摩托罗拉公司的芯片ＭＣ１３７７和ＭＣ１３７４组成的视频编码器和射频调制器接口，可产生相应的视频和射
1 Preface TV signal generator is necessary tests within the television industry, maintenance tools. MCS-51 microcontroller design TV signal generator can produce eight most commonly R, G, B, SYNG test signal. MC1377 and MC1374 by Motorola chip composed of a video encoder and a RF modulator interface can produce the corresponding video and radio (2012-11-01, Video, 34KB, 下载8次)

http://www.pudn.com/Download/item/id/2033906.html

[VHDL/FPGA/Verilog] OV76751.0-OVT

OV7675 中文SPEC 各類型寄存器值
OV7675 Chinese SPEC (2012-08-21, Video, 1436KB, 下载16次)

http://www.pudn.com/Download/item/id/1971819.html

[VHDL/FPGA/Verilog] CAVLC

关于自己在万方数据库上收集的近五年的CAVLC熵解码器设计的文档，用FPGA/VLSI实现
Articles database on their own in the collection of nearly five years of CAVLC entropy decoder design document, with FPGA/VLSI implementation (2011-08-25, Video, 15801KB, 下载19次)

http://www.pudn.com/Download/item/id/1630939.html

[VHDL/FPGA/Verilog] hd_source

基于Verilog HDL的视频测试pattern发生器。内置各种常见模式。
Verilog HDL-based video test pattern generator. Built-in a variety of common models. (2011-04-26, Video, 2KB, 下载17次)

http://www.pudn.com/Download/item/id/1507772.html

[VHDL/FPGA/Verilog] The-Design-of-Ethernet-MAC-

基于FPGA的以太网MAC控制器的设计，此文在以太网方面非常的好，有利天我国社会主义发展
This paper introduces the principles and types of animation，and and and three-dimensional animation，and the dimensional animation，etc． (2011-04-15, Video, 299KB, 下载18次)

http://www.pudn.com/Download/item/id/1492753.html

[VHDL/FPGA/Verilog] code

modelsim下的60进制计数器源码和测试激励文件
modelsim M counter 60 under the source file and test incentives (2009-07-17, Video, 3KB, 下载26次)

http://www.pudn.com/Download/item/id/847583.html

总计:11