Brief芯片是一个用Spinal HDL编写的简单Soc项目，包括一个3级RISCV CPU和一个以RS数据流为外围设备的CNN加速器
The Brief Chip is a Simple Soc project written in Spinal HDL , include a 3 stages RISCV CPU and a CNN Accelerator with RS Dataflow as Peripheral (2024-03-12, Scala, 0KB, 下载0次)
用于Intellij IDEA的SBT依赖性分析器，
SBT Dependency Analyzer for Intellij IDEA, (2023-08-04, Scala, 0KB, 下载0次)
嵌入式S3服务器，易于模拟，
Embedded S3 server for easy mocking, (2022-06-21, Scala, 0KB, 下载0次)
火花加速器，，
sparccelerator,, (2018-06-26, Scala, 0KB, 下载0次)
交通模拟器，
Transport Simulator, (2017-10-04, Scala, 0KB, 下载0次)
本回购协议旨在演示用Chisel编写的许多简单MIPS处理器。，
This repo has been put together to demonstrate a number of simple MIPS Processors written in Chisel., (2021-07-09, Scala, 0KB, 下载0次)
为IntelliJ添加语言服务器协议支持的插件
Plugin adding Language Server Protocol support for IntelliJ (2023-06-15, Scala, 11845KB, 下载0次)