以1HZ的时钟作为基准信号，测量10HZ~10MHZ的频率。在电路中，采用8个级联的模10计数器进行计数，8个模10计数器分别输出第1位至第8位的8421BCD码。
Using a 1HZ clock as a reference signal, a frequency of 10 Hz to 10 MHz is measured. In the circuit, eight cascaded modulo 10 counters are used for counting, and 8 modulo 10 counters output 8421 BCD codes of the first to eighth bits, respectively. (2018-05-15, Verilog, 1KB, 下载0次)
计数器跳跃进位加法器CLA代码，加法器计数器
adder with four 8-bit
groups. 8-bit adder will have two 4-bit groups. (2017-11-01, Verilog, 7KB, 下载4次)