为同步FIFO构建UVM环境。使用了虚拟定序器、重置代理、断言等概念。，
Build a UVM Environment for an a Synchronous FIFO. Concepts like virtual sequencer, reset agents, assertions were used., (2023-08-04, Verilog, 0KB, 下载0次)
平衡五级流水线MIPS处理器的设计与实现，确保使用流水线提高性能...
Design & Implementation of a balanced five stage pipelined MIPS Processor ensuring improved performance using pipelining & hazard control methods Tools and Languages: Synopsys Verilog Compiler Simulator (VCS), Synopsys Design Vision, Verilog (2015-09-21, Verilog, 7KB, 下载0次)
FPGA上的学期项目-用于边缘检测的Sobel滤波器在FPGA上的Verilog实现
Semester Project on FPGA - Verilog implementation on Sobel Filter for Edge detection on FPGA (2019-04-28, Verilog, 421KB, 下载0次)