数字环路滤波器的实现
Digital Loop Filter Realization (2023-12-23, Verilog, 0KB, 下载0次)
2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。,
2023 will set up the second world championship, and the purple light will create the cup together. A simple convolution layer accelerator based on systolic array writing, which supports the first layer convolution layer calculation of yolov3 tiny, and can flexibly adjust the structure of the systolic array according to the DSP resources on the FPGA side to achieve different computing efficiency., (2023-09-01, Verilog, 0KB, 下载1次)