这个项目利用状态机的方式实现简易计算器的功能，可以完成两个状态数和加减乘除四种基本运算, stars:1, update:2024-05-31 15:36:06 (2024-05-31, Verilog, 0KB, 下载0次)
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武汉大学计算机组成与设计课程单周期CPU处理器实现,使用RISC-V语言实现。
The course of Computer Composition and Design of Wuhan University is implemented with a single cycle CPU processor using RISC-V. (2024-03-14, Verilog, 0KB, 下载0次)
基于RISC-V的SHA系列算法硬件加速协处理器设计及实现
Design and Implementation of Hardware Acceleration Coprocessor for SHA Series Algorithms Based on RISC-V (2024-03-10, Verilog, 0KB, 下载0次)
使用Verilog设计单周期、多周期以及流水线处理器,完成计算工作以及IO仿真
Use Verilog to design single cycle, multi cycle and pipeline processors to complete computing and IO simulation (2023-12-31, Verilog, 0KB, 下载0次)
Verilog implementation of SHA1 SHA224 SHA256 SHA384 SHA512. 使用Verilog实现的SHA1 SHA224 SHA256 SHA384 SHA512计算器。
Verilog implementation of SHA1 SHA224 SHA256 SHA384 SHA512 The SHA1 SHA224 SHA256 SHA384 SHA512 calculator implemented by Verilog. (2023-09-14, Verilog, 0KB, 下载0次)
基于布尔函数的伪随机发生器的设计，
Design of a boolean function based pseudo random generator, (2023-09-30, Verilog, 0KB, 下载0次)
了解FemtoRV处理器，Bruno Levy，
Learning about the FemtoRV processor, by Bruno Levy, (2023-01-25, Verilog, 0KB, 下载0次)
用于求解4D Dubins Car系统上哈密顿-雅可比偏微分方程（PDE）的加速器，
Accelerators for solving Hamiltonian-Jacobi partial differential equation (PDE) on a 4D Dubins Car system, (2021-09-10, Verilog, 0KB, 下载0次)
可再现线性代数RISC-V张量核向量协处理器的事务Verilog设计和Verilator测试台，
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra, (2021-12-19, Verilog, 0KB, 下载0次)
DeBAM：低功耗应用中基于解码器的近似乘法器
DeBAM : Decoder Based Approximate multiplier for Low Power Applications (2021-02-20, Verilog, 0KB, 下载0次)
RTL设计：带2个ALU的流水线多端口计算器—一个用于加减运算，另一个用于移位运算。开发人员...
RTL Design: Pipelined Multi port Calculator with 2 ALUs one for Add/Subtract and other for Shift operations. Developed a Gray box model with on-the fly constraint random simulation generation. Used reference model based scoreboard technique with functional coverage to verify the DUV. Language used: System Verilog (2017-02-02, Verilog, 0KB, 下载0次)
动态时间规整(DTW)算法的硬件加速器,清华大学2021春集成电路课程设计大作业
Hardware accelerator of dynamic time warping (DTW) algorithm, Tsinghua University Spring 2021 Integrated Circuit Course Design assignment (2021-06-26, Verilog, 483KB, 下载0次)
高斯滤波器Verilog实现-，，
Gaussian-Filter-Verilog-Implementation-,, (2021-08-05, Verilog, 2507KB, 下载0次)
verilog实现自适应高斯滤波器。
Verilog implements adaptive gaussian filter. (2017-11-29, Verilog, 10990KB, 下载0次)
实现单精度浮点的kalman滤波器的verilog方法
Verilog method for realizing single precision floating point Kalman filter (2018-04-10, Verilog, 315KB, 下载17次)
介绍了一种利用FPGA硬件平台生成高斯随机数的算法
An algorithm for generating Gauss random numbers using FPGA hardware platform is introduced. (2017-10-11, Verilog, 32KB, 下载4次)