AI生成的Verilog RTL设计用于太阳能电池板监视器，
AI generated Verilog RTL design for Solar Panel monitor, (2023-10-29, Verilog, 0KB, 下载0次)
CNN硬件加速器，用于加速量化LeNet-5模型，
CNN hardware accelerator to accelerate quantized LeNet-5 model, (2023-09-20, Verilog, 0KB, 下载0次)
基于高斯混合模型分类器的高效FPGA实现，
An Efficient FPGA Implementation of Gaussian Mixture Models-Based Classifier, (2023-09-17, Verilog, 0KB, 下载0次)
可重构_加速器_发动机2023 6 22，
reconfigurable_accelerator_engine 2023 6 22, (2023-07-06, Verilog, 0KB, 下载0次)
可编程izhikevich峰值神经网络加速器的Verilog规范，
Verilog specification for a programmable izhikevich spiking neural network accelerator, (2019-12-03, Verilog, 0KB, 下载0次)
tinyODIN数字脉冲神经网络（SNN）处理器-HDL源代码和文档。，
tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation., (2023-03-30, Verilog, 0KB, 下载0次)
完全开源的峰值神经网络加速器，
Fully opensource spiking neural network accelerator, (2023-02-13, Verilog, 0KB, 下载0次)
ODIN在线学习数字脉冲神经网络（SNN）处理器-HDL源代码和文档。，
ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation., (2019-04-20, Verilog, 0KB, 下载0次)
这是es=2的32位位数字的精确乘法累加器的硬件实现，
This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2, (2018-01-27, Verilog, 0KB, 下载0次)
Ochiba是一款RISC-V RV32I兼容处理器，具有低LUT资源消耗和高频驱动。，
Ochiba is a RISC-V RV32I compatible processor featuring low LUT resource consumption and high frequency drive., (2018-05-19, Verilog, 0KB, 下载0次)
RISC-V处理器从头开始设计，具有流水线、转发、危险检测、基于神经元的感知器分支预测器、bran...，
RISC-V Processor designed from scratch featuring pipelining, forwarding, hazard detection, neuron-based perceptron branch predictor, branch target buffer, two-legel cache, victim cache, and negative-edge triggered memory arbiter. (2021-11-23, Verilog, 0KB, 下载0次)
FPGA上的Leaky集成和Fire spiking神经元可视化器（ICE40），
A Leaky integrate and Fire spiking neuron visualizer on an FPGA(ICE40), (2020-08-17, Verilog, 0KB, 下载0次)
具有Verilog和8个可用神经元的MNIST分类器FNN实现，
MNIST-Classifier-FNN Implementation with Verilog and 8 available neurons, (2022-02-02, Verilog, 0KB, 下载0次)
多层感知器（MLP）神经网络的硬件实现
Hardware implementation of a Multi-Layer Perceptron (MLP) Neural Network (2021-03-25, Verilog, 1560KB, 下载0次)
用于卷积层（卷积运算）和全连接层（矩阵乘法）的深度学习加速器...
Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication). (2018-11-18, Verilog, 6525KB, 下载0次)
深度学习加速器（卷积神经网络）
Deep Learning Accelerator (Convolution Neural Networks) (2017-12-15, Verilog, 138KB, 下载0次)
具有近似函数的32位RISC-V处理器
32 Bits RISC-V Processor with Approximate Functions (2023-05-26, Verilog, 100KB, 下载0次)
8x8重量固定式收缩阵列DNN加速器的FPGA实现
FPGA implement of 8x8 weight stationary systolic array DNN accelerator (2021-02-27, Verilog, 3089KB, 下载1次)
FPGA硬件中从AI模型到RTL（Verilog）加速器的编译器，具有自动设计空间探索功能。
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration. (2019-12-02, Verilog, 2140KB, 下载0次)
NutShellTeam,果壳处理器研究小组(Topic:基于RISCV64果核处理器的卷积神经网络加速器研究)
NutShellTeam, Fruit Shell Processor Research Group (Topic: Convolutional Neural Network Accelerator Research Based on RISCV64 Fruit Core Processor) (2022-05-28, Verilog, 17267KB, 下载0次)