This project focuses on the implementation of Direct Digital Synthesis (DDS) to generate sine waves using the lookup table (LUT) method, coupled with an 8-bit Digital-to-Analog Converter (DAC). (2024-05-24, Verilog, 0KB, 下载0次)
http://www.pudn.com/Download/item/id/1716520988265134.html
通过多个处理器访问内存位置。仲裁器接受四个输入请求并输出准予（一个热编码）信号。
Accessing a Memory location by multiple Processor. Arbiter takes four input requests and outputs a grant(ONE HOT ENCODED) signal. (2024-03-29, Verilog, 0KB, 下载0次)
使用FPGA创建一个简单的DDS信号发生器，可以产生四种波形：正弦波、方波、三角波和锯齿波，并可以调整幅度和频率。
Use FPGA to create a simple DDS signal generator that can generate four waveforms: sine wave, square wave, triangle wave, and sawtooth wave, and can adjust the amplitude and frequency. (2024-01-02, Verilog, 0KB, 下载1次)
信号处理加速器
Signal processing accelerator (2023-11-08, Verilog, 0KB, 下载0次)
一种高性能、独立驱动、噪声消除、基于斜交的压控环形振荡器，
A high-performance, separately driven, noise cancelling, skew-based Voltage Controlled Ring-Oscillator, (2021-12-12, Verilog, 0KB, 下载0次)
在FPGA上使用HC-SR04超声波传感器测量距离。，
Measure the distance using HC-SR04 ultrasonic sensor on FPGA., (2022-07-09, Verilog, 0KB, 下载0次)
超声波风速风向传感器，
Ultrasonic wind speed and direction sensor, (2020-01-10, Verilog, 0KB, 下载4次)
该方案是对使用开关闪烁led的基本介绍，因为开关是在板上机械操作的，所以同步器是u...，
This project is a basic introduction to blinking a led using switch as switches are mechanically operated in boards ,so synchronizer is used for the perfect operation of debouncing of a switch to turn the led on . It was designed in XILINX ISE 14.7 using Verilog HDL. (2022-03-02, Verilog, 0KB, 下载0次)
DDS频率控制寄存器可以串行或并行加载和存储用户输入的频率控制码...
The DDS frequency control register can load and store the user-entered frequency control code serially or in parallel, while the phase accumulator adds phases to each clock cycle according to the frequency control code to obtain a phase value, and the sine calculator calculates the digitized sine wave amplitude for that phase value (2021-11-15, Verilog, 17KB, 下载0次)
基于Cadence，，的正弦波发生器的实现与分析，，
Implementation-and-Analysis-of-Sine-Wave-Generator-using-Cadence,, (2023-04-08, Verilog, 769KB, 下载0次)
该存储库包含使用eSim的8位数字正弦波发生器的混合信号设计的尝试
This repository contains an attempt to mixed signal design of a 8-bit Digital Sine wave generator using eSim (2022-03-12, Verilog, 6534KB, 下载0次)