Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation. (2024-05-26, Verilog, 0KB, 下载1次)
http://www.pudn.com/Download/item/id/1716720994510511.html
灰色计数器是一种计数器，其中输出一次只改变一个位，相邻的数字只有...
A Gray counter is a type of counter in which the output changes only one bit at a time, and adjacent numbers have only a one-bit difference, making it useful in many applications such as digital signal processing and communication systems. (2023-04-29, Verilog, 0KB, 下载0次)
在Verilog中设计了一个数字信号处理器，以实现可编程无限脉冲响应（PIIR）滤波器。
Engineered a digital signal processor in Verilog to implement a Programmable Infinite Impulse Response (PIIR) filter. (2015-02-05, Verilog, 0KB, 下载0次)
有限脉冲响应-数字信号处理器
Finite Impulse Response - Digital Signal Processor (2012-05-15, Verilog, 0KB, 下载0次)
设计了一种支持CORDIC旋转奇异值分解的数字信号处理器
Designed a digital signal processor supporting Singular Value Decomposition through CORDIC rotation (2017-02-06, Verilog, 0KB, 下载3次)
FPGA上的实时语音声码器。我们的设计展示了一种建立在数字系统基础上的高度并行设计...
A real-time speech vocoder on an FPGA. Our design shows a highly parallel design built on the foundations of digital signal processing and CPU design. (2019-05-15, Verilog, 0KB, 下载0次)
高阶LC滤波器
3rd order LC filter
3rd order LC filter with subcircuit (2020-09-30, Verilog, 3KB, 下载0次)
经典的verilog语言实现直接型FIR滤波器的代码
Code of Direct FIR Filter Implemented by Classical Verilog Language (2019-03-19, Verilog, 279KB, 下载3次)
经典的对称性FIR滤波器传递函数verilog代码
Verilog code for transfer function of classical symmetric FIR filter (2019-03-19, Verilog, 296KB, 下载1次)
半带滤波器，工作在采样率122.88Msps上
Half-band filter, working at the sampling rate of 122.88 Msps (2019-03-11, Verilog, 5392KB, 下载2次)
基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。
The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations. (2019-01-06, Verilog, 3KB, 下载3次)
串行数据TTL 编码发送器使用verlog语言编写的。
Serial data TTL coded transmitter FPGA (2018-05-11, Verilog, 1KB, 下载0次)
四人抢答器，ax516开发板完成功能，基于verilog hdl
Four person responder (2017-11-06, Verilog, 4313KB, 下载3次)
依据卫星导航原理，通过Intel接口控制产生37颗北斗卫星对应的PRN（B1I）码。系统时钟10.023MHz
According to the principle of satellite navigation, the PRN (B1I) code corresponding to the 37 Beidou satellites is generated by the control of Intel interface. System clock 10.023MHz (2017-10-11, Verilog, 500KB, 下载2次)
RS（罗德施瓦茨）信号源，内部ARM波形文件，输出4倍采样率噪声信号。
AWGN模型。
A wave data file outputing a AWGN signal based on RS signal generator. (2017-07-06, Verilog, 497KB, 下载1次)