当前设计的视频数据路径包括视频TPG、VDMA（流到内存映射）、DDR、VDMA（内存映射到流）和视频屏幕显示（OSD）IP块。这些视频IP块中的每一个被动态地配置为处理帧速率和分辨率的各种组合。板载可配置时钟生成器（SI570）用于生成所需刷新率和分辨率的视频时钟。VDMA由一个TPG驱动，TPG具有一个到VDMA的AXI4流接口。VDMA核心以自由运行模式运行。由AXI VDMA读取的数据被发送到OSD。OSD核心的输出驱动一个板载高清媒体接口（HDMI) 视频显示通过彩色空间转换器与VTC块产生必要的定时信号。
This design uses four AXI Video Direct Memory Access (VDMA) cores to simultaneously move eight streams (four transmit video streams and four receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 24 data bits per pixel. Each AXI Video DMA core is driven from a video test pattern generator (TPG) with a Video Timing Controller (VTC) core to
set up the necessary video timing signals. Data read by each AXI Video DMA core is sent to a common Video On-Screen Display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The onboard HDMI video display interface is driven by the output of the Video On-Screen Display core with additional IP cores. (2020-05-08, Verilog, 3952KB, 下载3次)
当前设计的视频数据路径包括视频TPG、VDMA（流到内存映射）、DDR、VDMA（内存映射到流）和视频屏幕显示（OSD）IP块。这些视频IP块中的每一个被动态地配置为处理帧速率和分辨率的各种组合。板载可配置时钟生成器（SI570）用于生成所需刷新率和分辨率的视频时钟。VDMA由一个TPG驱动，TPG具有一个到VDMA的AXI4流接口。VDMA核心以自由运行模式运行。由AXI VDMA读取的数据被发送到OSD。OSD核心的输出驱动一个板载高清媒体接口（HDMI?) 视频显示通过彩色空间转换器与VTC块产生必要的定时信号。
The video datapath of the current design includes video TPG, VDMA (streaming to memory-mapped), DDR, VDMA (memory-mapped to streaming), and video onscreen display(OSD) IP blocks. Each of these video IP blocks are configured dynamically to process various combinations of frame rate and resolution. An onboard configurable clock generator (SI570) is used to generate the video clock for the desired refresh rate and resolution. The VDMA is driven from a TPG which has an AXI4-Stream Interface to VDMA. The VDMA core operates in free running mode. Data read by the AXI VDMA is sent to the OSD. The output of the OSD core drives an onboard High Definition Media Interface (HDMI) video display through the color space converter with a VTC block to generate the necessary timing signals. (2020-05-08, Verilog, 8733KB, 下载0次)
该设计使用8个AXI视频直接存储器访问（AXI VDMA）引擎同时移动16个流（8个传输视频流和8个接收视频流），每个流以1920 x 1080像素格式以60赫兹刷新率移动，每个像素24个数据位。此设计还具有额外的视频等效AXI流量，该流量由为1080p视频模式配置的四个LogiCORE AXI流量发生器（ATG）核心生成。ATG核心根据其配置生成连续的AXI流量。在本设计中，ATG被配置成以1080p模式生成AXI4视频流量。这使得系统吞吐量需求达到DDR的80%左右带宽。每个AXI VDMA由LogiCORE IP测试模式生成器（AXI TPG）核心驱动。AXI VDMA配置为在自由运行模式下运行。每个AXI VDMA读取的数据被发送到能够将多个视频流多路复用或叠加到单个输出视频流的通用视频屏幕显示（AXI OSD）核心。AXI OSD核心的输出驱动板载高清媒体接口（HDMI技术）视频显示接口通过RGB到YCrCb颜色空间转换器核心和逻辑核心IP色度重采集器核心。LogiCore视频定时控制器（AXI VTC）生成所需的定时信号。
The design uses eight AXI video direct memory access (AXI VDMA) engines to simultaneously move 16 streams (eight transmit video streams and eight receive video streams), each in 1920 x 1080 pixel format at 60 Hz refresh rate, and 24 data bits per pixel. This design also has additional video equivalent AXI traffic generated from four LogiCORE AXI Traffic Generator(ATG) cores configured for 1080p video mode. The ATG core generates continuous AXI traffic based on its configuration. In this design, ATG is configured to generate AXI4 video traffic in 1080p mode. This pushes the system throughput requirement to approximately 80% of DDR
bandwidth. Each AXI VDMA is driven from a LogiCORE IP Test Pattern Generator (AXI TPG)core. AXI VDMA is configured to operate in free running mode. Data read by each AXI VDMA is sent to a common Video On-Screen Display (AXI OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. (2020-05-08, Verilog, 13073KB, 下载4次)
该设计使用五个AXI视频直接存储器访问（VDMA）引擎同时移动
10个流（5个传输视频流和5个接收视频流），每个流为1920 x 1080p
格式，60赫兹刷新率，每像素高达32个数据位。每个VDMA都是由视频驱动的
带有视频定时控制器（VTC）块的测试模式生成器（TPG），以设置必要的
视频定时信号。每个AXI VDMA读取的数据被发送到一个通用的屏幕显示
（OSD）能够将多个视频流复用或叠加到单个输出视频的核心
溪流。OSD核心的输出驱动板上的DVI视频显示接口。
添加性能监视器块以捕获性能数据。全部10个视频流
由AXI VDMA块移动的数据块通过共享DDR3 SDRAM内存进行缓冲，并且
由微生物控制? 处理器。
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board.Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze processor. (2020-05-08, Verilog, 16621KB, 下载3次)