使用4:2压缩器的16位数据乘法器，
A 16-bit dadda multiplier using a 4:2 compressor, (2020-11-09, Verilog, 0KB, 下载0次)
8位和16位操作数的近似乘数，使用近似压缩器构建。，
Approximate Multipliers of 8bit and 16bit operands, built with approximate compressors., (2021-11-11, Verilog, 0KB, 下载0次)
16位DADDA乘法器设计，使用5:2压缩器作为主减速压缩器和4:2压缩机；和FullAdder和HalfAdd...，
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively. (2021-05-14, Verilog, 0KB, 下载0次)
利用verilog语言编写的十位全加器，可以实现十位二进制的加法。
We can realize the addition of ten - digit binary by using the ten - digit total adder in verilog language. (2018-09-10, Verilog, 470KB, 下载0次)