支持MS U模式和虚拟存储器访问的5级RV32I处理器的实现。
A implement of 5-stage RV32I processsor that support M S U mode and virtual memory access. (2024-01-11, Verilog, 0KB, 下载0次)
支持异常处理和虚拟内存的五周期RISC-V处理器(Soc),
Five-cycle RISC-V processor (Soc) that supports exception handling and virtual memory, (2021-01-09, Verilog, 0KB, 下载0次)
在Verilog中具有精确中断的简单流水线处理器,
Simple Pipelined processor with precise interrupts in Verilog, (2016-07-16, Verilog, 0KB, 下载0次)
简单的基于FIFO的USB主机控制器,
Simple FIFO-based USB Host Controller, (2020-04-26, Verilog, 0KB, 下载0次)