数字跑表
该跑表具有启动、复位、暂停、暂停后继续计时等功能
能显示的秒计数时间精确到小数点后第二位，即能显示**.**s
Digital running meter
The running meter has the functions of start, reset, pause and continue timing after pause
The second counting time that can be displayed is accurate to the second place after the decimal point, i.e. it can display * *. * * s (2020-06-21, Verilog, 479KB, 下载1次)
本文使用在开发板上实现DDR的读写。 FPGA如果需要对DDR进行读写，则需要一个控制器。根据官方的文档控制器的时序主要有三
This article uses the development board to achieve DDR reading and writing. FPGA requires a controller if it needs to read and write DDR. According to the official documentation, the timing of the controller is mainly three. (2018-12-30, Verilog, 984KB, 下载1次)
实现通过按键控制计时器，完成+1项，置零项等
Achieve button control timer, complete +1 items, nulling items, etc. (2018-10-18, Verilog, 33034KB, 下载1次)
简易计数器，通过数码管显示计数数值，显示当前数据
Simple calculator,Through the digital tube (2018-05-24, Verilog, 16KB, 下载0次)
大学生专业课的lab，用Verilog实现半加器
the necessary lab for college students to fulfill the function of half-adder (2018-05-01, Verilog, 809KB, 下载1次)
当定时器控制寄存器EX_CON的CNT_START信号为1时,32位定时器开始计数
ü 当计数值等于定时时间配置寄存器EX_TO,定时器变为0,此时定时器控制寄存
器EX_CON的INT_EN为1,OVFL_CLS信号为0时,定时器中断信号INT_B变为低
电平
ü 当定时器控制寄存器EX_CON的OVFL_CLS信号为1时,NT_B变为高电平
When the CNT_START signal of timer control register EX_CON is 1, the 32 bit timer starts counting.
U when the count value is equal to the time variable configuration register EX_TO, timer 0, timer control register at
When the INT_EN of the EX_CON is 1 and the OVFL_CLS signal is 0, the timer interrupt signal INT_B becomes low.
level
U OVFL_CLS signal when the timer control register EX_CON is 1, NT_B becomes high level (2018-04-10, Verilog, 1KB, 下载1次)
五级流水CPU设计
流水线是数字系统中一种提高系统稳定性和工作速度的方法，广泛应用于高档CPU的架构中。根据MIPS处理器的特点，将整体的处理过程分为取指令（IF）、指令译码（ID）、执行（EX）、存储器访问（MEM）和寄存器会写（WB）五级，对应多周期的五个处理阶段。一个指令的执行需要5个时钟周期，每个时钟周期的上升沿来临时，此指令所代表的一系列数据和控制信息将转移到下一级处理。
Five level flow CPU design (2018-04-02, Verilog, 4547KB, 下载15次)
数控分频器的verilog代码在eda上实现
verilog for numerical control divider (2018-01-11, Verilog, 2796KB, 下载2次)
基于Nexys4开发板的3-8译码器的实现
Implementation of 3-8 decoder based on Nexys4 development board (2017-12-24, Verilog, 486KB, 下载1次)
SRAM读写测试实例，每秒钟进行一次单字节的SRAM
读和写操作，用chipscope查看时序波形。
SRAM read and write test instances, each time a single byte SRAM
Read and write operations, use chipscope to see the timing waveform. (2017-09-06, Verilog, 1309KB, 下载3次)
蜂鸣器开关实例，拨码开关SW3的ON和OFF状态对应
控制蜂鸣器响或不响。
Buzzer switch example, dial code switch SW3 ON and OFF state corresponding
Controls whether the buzzer sounds or does not sound. (2017-09-06, Verilog, 121KB, 下载1次)