vivado实现计数器，适用于ego1开发板，已通过测试 (2022-06-07, Vivado, 1908KB, 下载1次)
http://www.pudn.com/Download/item/id/1654597560761742.html基于vivado的新手入门全加器设计源码 (2022-05-13, Vivado, 466KB, 下载0次)
http://www.pudn.com/Download/item/id/1652456100732365.html基于vivado的新手入门两位比较器设计。 (2022-05-13, Vivado, 486KB, 下载0次)
http://www.pudn.com/Download/item/id/1652456040598624.html
Verilog语言，基于赛灵思的A7-100T.高速AD 转换芯片和高速DA 转换芯片分别是AD9280 和AD9708。FPGA 产生正弦波变化的数字信号，经过DA 芯片后转换成模拟信号，将DA 的模拟电压输出端连接至AD 的模拟电压输入端，AD 芯片将模拟信号转换成数字信号，然后通过ILA 观察数字信号的波形是否按照正弦波波形变化。
The FPGA generates a digital signal with sine wave variation and converts it into an analog signal after passing through the DA chip, and connects the analog voltage output of the DA to the analog voltage input of the AD. The AD chip converts the analog signal into a digital signal, and then observes whether the waveform of the digital signal changes according to the sine waveform through the ILA. (2021-04-28, Vivado, 44369KB, 下载7次)
verilog语言实现D触发器，可在vivado运行
Verilog language to implement D trigger (2021-03-16, Vivado, 2KB, 下载0次)
CAN驱动器-MCP2515-接口程序-Verilog
Can driver - MCP2515 - interface program - Verilog (2020-11-08, Vivado, 9KB, 下载8次)
内部含3个模块，使用DDS产生200k与500k的正弦波，两者相加后过数字低通滤波（通带0-200k，阻带400k以上），并将波形输出，实测FFT分析中看不到500k分量。其中数字滤波器采用MATLAB设计（FIR+等波纹，阻带衰减-80dB）
There are three modules in the system. DDS is used to generate 200K and 500K sine waves. After adding the two modules, the digital low-pass filter (passband 0-200k, stopband above 400k) is used, and the waveform is output. 500K component can not be seen in the actual FFT analysis. The digital filter is designed by MATLAB (FIR + equal ripple, stopband attenuation - 80dB) (2020-09-09, Vivado, 40691KB, 下载2次)
使用FPGA的verilog语言编码测试DDS芯片，让其产生良好信号波形
Testing DDS with FPGA (2020-04-26, Vivado, 11941KB, 下载25次)
实现8路并行dds的功能，可以提高dds的速率
Realizing the function of 8 parallel DDS can improve the speed of DDS (2020-04-20, Vivado, 1KB, 下载1次)
实现位流水灯，使其按顺序闪烁，可以显示仿真波形,源文件和激励文件已经设置好
Through vivado, the 16 bit running water lamp can flash in order, and the simulation waveform can be displayed (2020-03-10, Vivado, 669KB, 下载2次)
该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程
This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process (2019-12-14, Vivado, 6144KB, 下载10次)
实现了一个简易滤波器，可以对模拟波形进行滤波
A simple filter is implemented to filter analog waveforms (2019-06-17, Vivado, 517KB, 下载0次)
序列发生器就是 随着时钟的变化，循环发送一个序列：11001 11001 11001….
触发器就是随着时钟的变化，状态在循环改变
一个循环需要五个状态，用三个二进制组成八个状态，取前五个来用。
Sequence generator is to send a sequence with the change of clock: 11001 11001 11001. . A trigger is a state that changes in a loop as the clock changes. A cycle needs five states, which are composed of three binaries and eight states, and the first five are used. (2019-04-16, Vivado, 434KB, 下载1次)
同步T触发器及仿真，可运行。实现平台为vivado，语言为Verilog，实现了一个简单的T触发器，有仿真代码和仿真波形图
Synchronous T flip-flop (2018-08-08, Vivado, 50KB, 下载0次)
在vivado上测试通过的fpga分频器
FPGA frequency divider tested on vivado (2017-12-26, Vivado, 3KB, 下载11次)
在vivado上测试通过的fpga抢答器
Test the FPGA responder passed on vivado (2017-12-26, Vivado, 2KB, 下载25次)
8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件
8 bits counter,include v and testbech files ,has the ability of 8 bits counter (2017-12-17, Vivado, 14KB, 下载5次)
流水灯，译码器，编码器等实现的源代码和顶层文件。还包括测试文件。
Water lights, decoders, encoders and other source code and the top file. Also includes test files. (2017-11-12, Vivado, 1KB, 下载1次)
扰码器的FPGA实现，选择的扰码器规格为15位移位寄存器。
FPGA scrambler, scrambler specifications for a 15 bit shift register. (2017-10-26, Vivado, 31KB, 下载11次)