[硬件设计] fpga- 序列发生器

序列发生器就是 随着时钟的变化，循环发送一个序列：11001 11001 11001…. 触发器就是随着时钟的变化，状态在循环改变 一个循环需要五个状态，用三个二进制组成八个状态，取前五个来用。
Sequence generator is to send a sequence with the change of clock: 11001 11001 11001. . A trigger is a state that changes in a loop as the clock changes. A cycle needs five states, which are composed of three binaries and eight states, and the first five are used. (2019-04-16, Vivado, 434KB, 下载1次)