基于Verilog的timer计时器，start开始，到达设置计时点时输出一个高电平up信号
Timer timer based on Verilog, start, output a high-level up signal when it reaches the set time point (2021-04-21, Quartus II, 7883KB, 下载0次)
按一定的频率递增（0-999）
把计数值显示在数码管上
Increasing at a certain frequency (0-999)
Display the count on the digital tube (2017-12-14, Quartus II, 7919KB, 下载3次)
一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位
输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN.
A 2 bit BCD code decimal adder counter circuit, the input is the clock signal CLK, carry
The input signal CIN, each BCD code decimal adder counter output signal is D, C, B, A and carry output signal COUT, input clock signal CLK with fixed clock, carry input signal CIN. (2017-11-14, Quartus II, 1354KB, 下载2次)