显示器 vga彩条显示 verilog代码实现
Display VGA color bar (2021-04-01, Quartus II, 7365KB, 下载0次)
实现8位全加器，有进位信号输出，vhdl语言，已验证
The implementation of 8-bit full adder, carry signal output, VHDL language, has been verified (2020-07-21, Quartus II, 357KB, 下载0次)
实现matlab与fpga间uart通信，fpga控制fpga中的DAC产生特定波形，形成波形产生器
The UART communication between MATLAB and FPGA is realized. FPGA controls DAC in FPGA to generate specific waveform and forms waveform generator (2020-07-21, Quartus II, 350KB, 下载2次)
了解四位全加器的工作原理，进一步熟悉QUARTUS II软件的使用方法和VERILOGHDL输入，了解了宏功能模块的调用，实现四位全加器的宏功能调用。
Understand the working principle of the four bit full adder, further understand the use method of Quartus II software and VerilogHDL input, understand the call of macro function module, and realize the macro function call of the four bit full adder. (2020-06-01, Quartus II, 288KB, 下载0次)
用quartus Ⅱ实现4位全加器，六选一数据选择器仿真
The realization of 4-bit full adder with Quartus II and the simulation of one out of six data selector (2020-05-26, Quartus II, 9435KB, 下载0次)
实现串行的信号，低通fir滤波器，抽样8.182MHZ，
Realize serial signal, fir filter (2020-05-25, Quartus II, 4221KB, 下载1次)
dds设计仿真，包含matlab设计，modelsim仿真和verilog代码
DDS design simulation, including matlab design, Modelsim simulation and Verilog code (2020-04-01, Quartus II, 27833KB, 下载5次)
quartus 18.1河蟹文件，仅用于学习，不用于商业目的。
Quartus 18.1 crab file, for learning only, not for business purposes. (2019-11-07, Quartus II, 146KB, 下载17次)
全加器通过控制按键来控制led的亮灭，led的亮灭反应按键的数字
The full adder controls the number of the led's light-out and the response key of the led's light-out by controlling the key. (2019-06-11, Quartus II, 153KB, 下载0次)
加法器的封装
1.设计1位全加器
2.将1位全加器扩展为4位全加器
3.使4位的全加器能做加减法运算
Packaging of adder
Design of 1-bit full adder
Expanding 1-bit full adder to 4-bit full adder (2019-03-12, Quartus II, 9230KB, 下载0次)
用EDA语言实现16进制计数器，代码及其仿真结果，并能在实际器件中完成数码管的16进制计数器功能的实现
Using EDA language to achieve 16 binary counter, code and its simulation results, and in the actual device to complete the digital tube of the 16 counter function. (2019-03-07, Quartus II, 1494KB, 下载0次)
显示器EDID官方标准，可进行编程指导。
E-EDID standard can used prorgram. (2018-10-30, Quartus II, 129KB, 下载1次)
做的一个简单计价器，有切换白天晚上不同计价的功能，而且自带暂停键，自带计时功能。非常好用，而且超级简单
A simple meter is used to switch functions of different days during the day. It also has its own pause key and its own timer function. Very good, and super simple (2018-07-23, Quartus II, 5115KB, 下载0次)
M5计时器,可拓展用于数码管显示，以及课程设计中提供分块代码的实现思路
M5 timer can be extended for digital tube display, and the realization of block code in course design (2018-07-09, Quartus II, 153KB, 下载1次)
原码一位乘法运算器，在不需要什么说明了都在代码里
A multiplicator of the original code (2018-05-09, Quartus II, 1836KB, 下载3次)
熟悉使用蜂鸣器以及DSP28335,用DSP28335控制蜂鸣器唱歌
Be familiar with buzzer and DSP28335, and use DSP28335 to control the buzzer (2018-01-30, Quartus II, 121KB, 下载4次)
计数器 12位 可逆 进位
Counter (2017-12-25, Quartus II, 2727KB, 下载1次)
使用FPGA的verilog语言生成方波调制波形
To generate square wave (2017-12-05, Quartus II, 3924KB, 下载2次)
The output frequency requirements for the three waveforms are: the frequency range is adjustable between 20Hz-20kHz; the phase difference between the three waveforms is 120 degrees.
A. of sine wave signal: step 10Hz; frequency stability: better than 1/10000; nonlinear distortion coefficient is less than 3%.
B. of the square wave signal is frequency: the rise and fall time of <1 s;
The requirements of C. for triangular wave signals are that the signal frequency range is adjustable between 20Hz-20kHz.
D. for the above three frequencies are required: the frequency can be preset; when the load is 600, the output signal amplitude is greater than 3V; the output signal amplitude can be adjusted in the range of 100mv~3V, the step length is 100mV.
The output frequency requirements for the three waveforms are: the frequency range is adjustable between 20Hz-20kHz; the phase difference between the three waveforms is 120 degrees.
A. of sine wave signal: step 10Hz; frequency stability: better than 1/10000; nonlinear distortion coefficient is less than 3%.
B. of the square wave signal is frequency: the rise and fall time of <1 s;
The requirements of C. for triangular wave signals are that the signal frequency range is adjustable between 20Hz-20kHz.
D. for the above three frequencies are required: the frequency can be preset; when the load is 600, the output signal amplitude is greater than 3V; the output signal amplitude can be adjusted in the range of 100mv~3V, the step length is 100mV. (2017-10-05, Quartus II, 352KB, 下载1次)
十二进制计数器，基于verilog HDL实现。
Twelve decimal counter (2017-09-19, Quartus II, 3112KB, 下载1次)