[VHDL/FPGA/Verilog] cordic_dds
采用CORDIC算法的直接数字频率合成器的设计
CORDIC algorithm uses direct digital frequency synthesizer design (2015-08-18, Unix_Linux, 230KB, 下载10次)
[VHDL/FPGA/Verilog] IXP2400_HardwareRefManual
intel ixp2400 硬件手册，主要包含处理器的相关硬件单元，如ddr 控制器，sram控制器，pci单元等
intel ixp2400 hardware manuals related hardware unit mainly includes a processor, such as ddr controller, sram controller, pci unit, etc. (2015-07-10, Unix_Linux, 2668KB, 下载1次)
[VHDL/FPGA/Verilog] RS_enc
RS编码器设计，使用Verilog实现。
RS encoder design, Verilog implementation. (2014-12-18, Unix_Linux, 15KB, 下载4次)
[VHDL/FPGA/Verilog] oms_check_host
在本地按计划自动连接到远端服务器，在远端服务器上执行相应命令来获取磁盘和CPU状态信息。
On local host,to get the information of remotely host disk ang CPU status. (2014-10-22, Unix_Linux, 2KB, 下载2次)
[VHDL/FPGA/Verilog] timer
基于sanxing A8的定时器控制led灯
can make time (2013-08-10, Unix_Linux, 9KB, 下载2次)
[VHDL/FPGA/Verilog] fpga
嵌入式fpga示波器采集配置及源码
采用keil4，兴建工程
The embedded FPGA oscilloscope acquisition configuration and source (2013-04-22, Unix_Linux, 3977KB, 下载28次)
[VHDL/FPGA/Verilog] digital-filter
数字滤波器的设计丛书，基于FPGA的设计
book for digital filter design (2012-07-19, Unix_Linux, 567KB, 下载3次)
[VHDL/FPGA/Verilog] XINHAO
简易的信号发生器常见波形的VHDL编写程序。
Common waveform signal generator VHDL programming. Common waveform signal generator VHDL programming. (2012-04-30, Unix_Linux, 1KB, 下载4次)
[VHDL/FPGA/Verilog] counter
fpga实现的计数器。。。。。。。。。。。。。。。。
fpga implementation of the counter。。。。。。。。 (2010-12-17, Unix_Linux, 2KB, 下载9次)
[VHDL/FPGA/Verilog] VHDL_implementation_1KHz_sine_wave_generator
用VHDL实现1KHz正弦波发生器，编译器是Quartus II 5.4
1KHz sine wave generator using VHDL implementation, the compiler is a Quartus II 5.4 (2010-01-21, Unix_Linux, 183KB, 下载5次)
[VHDL/FPGA/Verilog] CICverilog
CIC滤波器的veilog代码,需要的硬件少。
CIC digital filter code (2009-08-18, Unix_Linux, 2KB, 下载12次)
[VHDL/FPGA/Verilog] PROJ
1、本实验模拟正弦函数发生器
2、使用逻辑分析仪查看波形
3、/proj/simulation目录中可以在modelsim中仿真
1, this experiment simulated sine function generator 2, using the logic analyzer to view waveform 3,/proj/simulation directory of simulation in modelsim (2009-07-09, Unix_Linux, 1123KB, 下载2次)
[VHDL/FPGA/Verilog] FPGA_FIR_filter
优秀论文,基于FPGA的FIR滤波器的设计
FPGA-based FIR filter design (2009-05-07, Unix_Linux, 384KB, 下载66次)
[VHDL/FPGA/Verilog] 200881022729529
eda出租车计价器的实现,实现计费,路程,速度,
EDA Taximeter realization, the realization of billing, distance, speed, (2009-01-15, Unix_Linux, 207KB, 下载21次)
[VHDL/FPGA/Verilog] 用一位全加器组成四位全加器
用一位全加器组成四位全加器.
所用语言是Verilog HDL.
主要用在加法器的设计中。
All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design. (2006-01-14, Unix_Linux, 3KB, 下载45次)
[VHDL/FPGA/Verilog] D触发器的设计
D触发器的设计
主要用在时序电路中。
所用语言为Verilog HDL.
D flip-flop with the main design of the timing circuit. The language used for Verilog HDL. (2006-01-14, Unix_Linux, 3KB, 下载51次)
[VHDL/FPGA/Verilog] 异步FIFO存储器的控制设计
异步FIFO控制器的设计
主要用于异步先进先出控制器的设计。
所用语言Verilog HDL.
asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL. (2006-01-14, Unix_Linux, 6KB, 下载407次)
[VHDL/FPGA/Verilog] counter10
该程序实现的是10进制的计数器，具有置位复位的功能。
the program is the band of 10 counters, with the home-reset function. (2005-11-15, Unix_Linux, 13KB, 下载12次)
[VHDL/FPGA/Verilog] sub_full_n
该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。
Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices. (2005-11-15, Unix_Linux, 26KB, 下载39次)
[VHDL/FPGA/Verilog] add_full_n
该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。
the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder. (2005-11-15, Unix_Linux, 21KB, 下载19次)