?用计数器（移位寄存器）和数据选择器设计一个具有自启动功能的01011序列信号发生器。
? 要求:
?（1）写出设计过程，画出逻辑电路图
?（2）加入连续时钟脉冲，用示波器观察并记录时钟脉冲CLK、序列输出端的波形；
A 01011 sequence signal generator with self starting function is designed with counter (shift register) and data selector.
Requirements:
(1) write the design process and draw the logic circuit diagram
(2) add the continuous clock pulse, observe and record the clock pulse CLK and the waveform of the sequence output terminal with an oscilloscope; (2020-07-03, Multisim, 142KB, 下载0次)
用双四选一数据选择器74LS153设计一个全加器。设计测试电路，记录全加器的真值表。
A full adder is designed with 74LS153, a double four out of one data selector. Design the test circuit and record the truth table of full adder. (2020-07-03, Multisim, 86KB, 下载0次)
二极管平衡混频电路，单调谐回路放大器，二极管平衡混频器，高频功率放大器，惰性失真，负峰切割失真
Multisim experimental circuit (2018-10-25, Multisim, 2257KB, 下载15次)