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按分类查找All VHDL/FPGA/Verilog(11) 
按平台查找All C++ Builder(11) 

[VHDL/FPGA/Verilog] FIR

了解FIR滤波器的工作原理,并通过编程学会怎么运用FIR滤波器。
Learn how the FIR filter, and how to learn programming through the use of FIR filters (2016-03-15, C++ Builder, 320KB, 下载2次)

http://www.pudn.com/Download/item/id/1458007770536863.html

[VHDL/FPGA/Verilog] uart_verilog

UART串口通信代码,FPGA编程,用Verilog代码编写
UART serial communication code, FPGA programming with Verilog coding (2013-09-14, C++ Builder, 10KB, 下载8次)

http://www.pudn.com/Download/item/id/2355142.html

[VHDL/FPGA/Verilog] i2c

iic总线编写例,可以借鉴使用,编程Verilog语言。
iic bus prepare cases, you can learn to use Verilog programming language. (2013-09-14, C++ Builder, 713KB, 下载2次)

http://www.pudn.com/Download/item/id/2355141.html

[VHDL/FPGA/Verilog] WDS_PMT

光谱分析仪程序,编程语言为C++Builder,重点在于对光学仪器中的数据采集和分析
Spectrum analyzer program, programming languages ​ ​ C++Builder, focused on the collection and analysis of data in optical instruments (2012-12-25, C++ Builder, 804KB, 下载50次)

http://www.pudn.com/Download/item/id/2095614.html

[VHDL/FPGA/Verilog] Foreign-language-translation

本系统由霍尔传感器、RC滤波电路、单片机AT89S51、系统化LED显示模块、数据存储电路和键盘控制组成。其中霍尔传感器包含信号放大和波形整形。对待测信号进行放大的目的是降低对待测信号的幅度要求;波形变换和波形整形电路则用来将放大的信号转换成可与单片机相连的TTL信号;通过单片机的设置可使内部定时器T1对脉冲输入引脚T0进行控制,这样能精确地算出加到T0引脚的单位时间内检测到的脉冲数;设计中速度显示采用LED模块,通过速度换算得来的里程数采用I2C总线并通过E2PROM来存储,既节省了所需单片机的口线和外围器件,同时也简化了显示部分的软件编程
The design of the bicycle odometer (2012-05-31, C++ Builder, 13KB, 下载4次)

http://www.pudn.com/Download/item/id/1896714.html

[VHDL/FPGA/Verilog] The-design-of-the-bicycle-odometer

本系统由霍尔传感器、RC滤波电路、单片机AT89S51、系统化LED显示模块、数据存储电路和键盘控制组成。其中霍尔传感器包含信号放大和波形整形。对待测信号进行放大的目的是降低对待测信号的幅度要求;波形变换和波形整形电路则用来将放大的信号转换成可与单片机相连的TTL信号;通过单片机的设置可使内部定时器T1对脉冲输入引脚T0进行控制,这样能精确地算出加到T0引脚的单位时间内检测到的脉冲数;设计中速度显示采用LED模块,通过速度换算得来的里程数采用I2C总线并通过E2PROM来存储,既节省了所需单片机的口线和外围器件,同时也简化了显示部分的软件编程
The design of the bicycle odometer (2012-05-31, C++ Builder, 206KB, 下载8次)

http://www.pudn.com/Download/item/id/1896697.html

[VHDL/FPGA/Verilog] counter-interrupt-8-timer-04s

单片机源程序(keilC语言)---计数器中断8次定时04s件,不需编程,但仅是对霍尔传感器测速应用的验证。
SCM source (keilC language)--- counter interrupt 8 timer 04s (2012-05-31, C++ Builder, 8KB, 下载7次)

http://www.pudn.com/Download/item/id/1896665.html

[VHDL/FPGA/Verilog] Hall-element-tachometer-circuit

下面以常见的玩具电机作为测速对象,用CS3020设计信号获取电路,通过电压比较器实现计数脉冲的输出,既可在单片机实验箱进行转速测量,也可直接将输出接到频率计或脉冲计数器,得到单位时间内的脉冲数,进行换算即可得电机转速。这样可少用硬件,不需编程,但仅是对霍尔传感器测速应用的验证。
Hall element tachometer circuit (2012-05-31, C++ Builder, 60KB, 下载3次)

http://www.pudn.com/Download/item/id/1896648.html

[VHDL/FPGA/Verilog] AD603

AD603的程序,AD603的基于FPGA的编程文件,并希望后者学者希望份额AD603verilog语言
AD603 program, the file on the AD603 FPGA-based programming, and hope that the latter scholars want AD603verilog languages ​ ​ share (2012-05-07, C++ Builder, 3KB, 下载9次)

http://www.pudn.com/Download/item/id/1858728.html

[VHDL/FPGA/Verilog] 20110126113917873

A/D转换芯片TLC2543的verilog编程,根据TLC5243的datasheet编写,程序简单,结构清晰,可以借鉴应用
A/D converter chip TLC2543 the verilog programming (2011-07-21, C++ Builder, 1KB, 下载43次)

http://www.pudn.com/Download/item/id/1603302.html

[VHDL/FPGA/Verilog] FCS

LabVIEW中所有这些能力的最终结果就是极大地提高了效率。许多方面的证据表明相对于传统编程工具效率提高了4到10倍。因此,这可能是导致不将LabVIEW视为一种通用的编程语言的最主要的原因。它是一个更高级的设计工具,从台式机器到嵌入式处理器,再到FPGA
yet few people realize it was originally developed by scientists to study spin and demonstrate that the Earth is rotating. Close observation of the astonishing behavior of gyroscopes led scientists to (2010-12-10, C++ Builder, 9KB, 下载4次)

http://www.pudn.com/Download/item/id/1375758.html
总计:11