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[VHDL/FPGA/Verilog] TornadoVM

TornadoVM:一种实用高效的托管语言异构编程框架
TornadoVM: A practical and efficient heterogeneous programming framework for managed languages (2023-05-30, Java, 5782KB, 下载0次)

http://www.pudn.com/Download/item/id/1685433960156355.html

[VHDL/FPGA/Verilog] MHDL

我的VHDL类编程语言为我的模块制作
My VHDL like programming language made for mine modus (2015-01-28, Java, 8KB, 下载0次)

http://www.pudn.com/Download/item/id/1422444377636697.html

[VHDL/FPGA/Verilog] aspectv

面向方面的vhdl编程
aspect oriented programming for vhdl (2017-03-25, Java, 114KB, 下载0次)

http://www.pudn.com/Download/item/id/1490452828848292.html

[VHDL/FPGA/Verilog] Assembler-Linker-for-MIPS

一个简单的汇编程序和链接程序,输出可以加载到VHDL MIPS处理器中的二进制代码。
A simple Assembler and Linker program which outputs binary code that can be loaded into a VHDL MIPS processor. (2015-03-03, Java, 49KB, 下载0次)

http://www.pudn.com/Download/item/id/1425375310739780.html

[VHDL/FPGA/Verilog] yahdl

FPGA的一种编程语言。
A programming language for FPGAs. (2018-05-05, Java, 34KB, 下载0次)

http://www.pudn.com/Download/item/id/1525526324736715.html

[VHDL/FPGA/Verilog] eclispe

随着对信息化及硬件设备的发展,人们对verilog HDL的使用逐步的用的更加频繁。然而目前的verilog HDL 编辑工具发展相对落后。限制了硬件编程的效率,所以本次通过这些插件的设计可以强大Eclipse的实用功能,使硬件编辑工具有更高的效率。在充分研究Eclipse IDE环境基础上,实现Verilog HDL插件移植,并能实现优惠插件设计实现,参照该环境下Java程序编写中出现的界面优化技术,关键字插件设计,模块查询插件设计等功能。提高硬件语言在该环境下的编程效率。并通过最终对Verilog HDL编写中关键字设计、界面优化技术实现的验证。旨在使Verilog HDL的使用更加方便,并为进一步的应用开发打下基础。
With information technology and hardware development, people use verilog HDL gradually with the more frequent. However, there is a verilog HDL editing tools is relatively undeveloped. Limiting the hardware programming efficiency, so these useful features of this powerful Eclipse plug-ins designed to make hardware more efficient editing tools. Eclipse IDE environment in the full study, based on Verilog HDL realize plug-transplant, and to achieve preferential plug-in design implementation, optimization techniques, keyword plug-in design, modular plug-in design features such as reference inquiries under the Java programming environment in the screen that appears. Improve the efficiency of hardware-language programming in the environment. And ultimately Verilog HDL prepared by keyword design, interface optimization technology validation. Designed to make it easier to use Verilog HDL, and lay the foundation for further application development. (2015-06-11, Java, 284KB, 下载1次)

http://www.pudn.com/Download/item/id/1433985578674838.html

[VHDL/FPGA/Verilog] CICS

cics编程基础的介绍, 这个为第一部分。
cics programming based introduction, this is the first part. (2013-08-09, Java, 3164KB, 下载5次)

http://www.pudn.com/Download/item/id/2326408.html
总计:8