可编程源代码,基于Verilog的程序,西电2013秋学期最新版上课要求自编的程序,txt文件
Programmable source code, Verilog-based program, Western Electric 2013 autumn semester class requires the latest version of the program self (2014-03-16, TEXT, 2KB, 下载1次)
本文章是基于ARM和FPGA的电脑刺绣机设计,希望对从事电脑刺绣机行业的编程开发人员有所帮助
This is a article about the design of computer embriodery machine based on the ARM and FPGA (2013-08-28, TEXT, 4KB, 下载13次)
vhdl编程风格与综合,大家可以看一下,觉得还可以
VHDL programming style and comprehensive, we can look at that can also be (2007-11-03, TEXT, 2KB, 下载2次)
使用Verilog硬件描述语言编程的38译码器,包含测试描述
Using Verilog hardware description language programming decoder 38 contains the test description (2007-08-10, TEXT, 68KB, 下载26次)
按键输入模块(key):
--可编程延时发生器(数字同步机)的前端输入模块:0-9十个数字键按键输入模块原型
--前端模块:消抖
--对i0-i9十个输入端的两点要求:
--(1)输入端要保证一段时间的稳定高电平
--(2)不能同时按下两个或多于两个的键
--后级模块:1、编码;2、可变模计数器
--编码模块:8线-4线(0-8 BCD码)
--可变模计数器模块:以编码模块输出的32位BCD码为模值
button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die (2005-09-01, TEXT, 2KB, 下载50次)