设计了一个6层楼的电梯控制器。该控制器可控制电梯完成6层楼的载客服而且遵循方向优先原则，并能响应提前关门延时关门，并具有超载报警和故障报警；同时指示电梯运行情况和电梯内外请求信息。
其中电梯控制方式为：
1.内部请求优先控制方式
2.单向层层停控制方式
3.方向优先控制方式
A six floor elevator controller is designed. The controller can control the elevator to finish the customer service of six floors and follow the principle of direction priority. It can respond to the door closing delay in advance, and has overload alarm and fault alarm. At the same time, it can indicate the operation of the elevator and the request information inside and outside the elevator.
The elevator control mode is:
1. Internal request priority control method
2. One way layer by layer stop control mode
3. direction priority control mode (2020-03-13, VHDL, 931KB, 下载5次)
a）以约 100KSPS 的采样率，连续对直流电压进行 AD 转换，将串行结果转换成并行，
显示在数码管上，测量三个以上电压点，分析 ADC 精度。
b）输入信号为 100Hz、幅度约 4.5V 的正极性正弦信号，用 SignalTap II 逻辑分析
仪分析转换结果。
c）实现单次 AD 转换：每按一次键，自动产生CS和一组时钟完成一次转换，将转换结
果显示在数码管上。
a) sampling rate of about 100KSPS continuous DC voltage for AD conversion, the conversion result of the serial to parallel,
Displayed on the digital tube, measuring more than three voltage points, analyze ADC accuracy.
b) the input signal is a sinusoidal signal of positive polarity 100Hz, amplitude approximately 4.5V, with the SignalTap II logic analyzer
Analyzed the conversion result.
c) achieve a single AD conversion: Each time you press the button, and automatically generates a set of CS clock to complete a conversion, the conversion result
Results are displayed on digital. (2014-03-26, VHDL, 328KB, 下载3次)
ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。
在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信）
ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from the control on the temperature, humidity, photoresistors, thermistors, and other information (including the main control machine from the control machine by zigbee protocol communications) (2012-05-18, VHDL, 1356KB, 下载23次)
以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字
滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了
对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结
果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求
W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has
developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is
show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on
FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design
requirement . (2011-04-20, VHDL, 15KB, 下载62次)
高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。
):
1统控制的电梯往返于1-9层楼。
2客要去的楼层数可手动输入并显示（设为A数）。
3梯运行的楼层数可自动显示（设为B数）。
4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；
当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；
当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门；
5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。
注：此为word文档，但里面有源代码。
High-rise elevator control system (Windows platform programming software running on the ispLEVER.
):
An elevator control system and from 1-9 floors.
2, the number of passengers going to the floor can manually enter and display (Make A number).
3 ladder run automatically display the number of floors (Set B number).
4A> B, the system can output three-phase motor is transferred to the timing signal to lift up
When A <B, the system can output three-phase motor to reverse the timing signal to the lift down
When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door
5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch.
Note: This is a word document, but inside the source code. (2010-06-10, VHDL, 34KB, 下载19次)
数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成
果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用
并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。
NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems. (2009-04-11, VHDL, 170KB, 下载42次)