该应用程序是一个旅游网站，允许您登录、过滤、搜索、排序酒店，并选择所需的酒店或在地图上指定您最喜欢的地方。通过HTML、CSS和React.js实现。在这个项目中，我使用json API处理数据，Axios库用于发布，并从json数据中获得它们，我还使用了React路由器dom和上下文。本项目
This app is a tourism site that allows you to log in, filter, search, sort hotels, and choose the desired hotel or specify your favorite places on the map. Implement by HTML, CSS, and React.js. In this project I used json API for data with Axios library for post and got them from the json data also I used react router dom and context. This projec (2024-01-29, JavaScript, 0KB, 下载0次)
该项目包含科罗拉多大学博尔德分校和Embry-Riddle航空公司的研究团队开发的代码...
This project contains code developed by a research team at University of Colorado,Boulder and Embry Riddle Aeronautical University to explore FPGA and GP-GPU co-processor power efficiency for continous transform 3D mapping and sensor fusion. Please use at your own risk. We are sharing so that other researchers and developers can recreate our (2016-12-02, C++, 15631KB, 下载0次)
设计了一个6层楼的电梯控制器。该控制器可控制电梯完成6层楼的载客服而且遵循方向优先原则，并能响应提前关门延时关门，并具有超载报警和故障报警；同时指示电梯运行情况和电梯内外请求信息。
其中电梯控制方式为：
1.内部请求优先控制方式
2.单向层层停控制方式
3.方向优先控制方式
A six floor elevator controller is designed. The controller can control the elevator to finish the customer service of six floors and follow the principle of direction priority. It can respond to the door closing delay in advance, and has overload alarm and fault alarm. At the same time, it can indicate the operation of the elevator and the request information inside and outside the elevator.
The elevator control mode is:
1. Internal request priority control method
2. One way layer by layer stop control mode
3. direction priority control mode (2020-03-13, VHDL, 931KB, 下载5次)
想法換位思考，感受與理解！
一人請一個瞎子朋友吃飯，吃的很晚，瞎子說很晚了我要回去了，主人就給他點了一個燈籠，他就很生氣的說：「我本來就看不見，你還給我一個燈籠，這不是嘲笑我嗎？」
主人說：「因為我在乎你才給你點個燈籠，你看不見，別人看得見，這樣你走在黑夜裡就不怕別人撞到你了，瞎子很感動！ 」
理解不同，結果就不一樣，我們要學會換位思考。每一件事用不同角度看，就會有不同的見解！
Soldiers training, no one dared to parachute, the instructor's face was ugly. Then someone saw that someone was laughing. The instructor said to the snicker: "What are you laughing..." Hey, he took him down with one foot. . (2019-03-06, Verilog, 4463KB, 下载0次)
Xilinx 关于PCIE读写控制的官方例程。
Xilinx PCIE Demo (2016-10-21, VHDL, 13345KB, 下载42次)
a）以约 100KSPS 的采样率，连续对直流电压进行 AD 转换，将串行结果转换成并行，
显示在数码管上，测量三个以上电压点，分析 ADC 精度。
b）输入信号为 100Hz、幅度约 4.5V 的正极性正弦信号，用 SignalTap II 逻辑分析
仪分析转换结果。
c）实现单次 AD 转换：每按一次键，自动产生CS和一组时钟完成一次转换，将转换结
果显示在数码管上。
a) sampling rate of about 100KSPS continuous DC voltage for AD conversion, the conversion result of the serial to parallel,
Displayed on the digital tube, measuring more than three voltage points, analyze ADC accuracy.
b) the input signal is a sinusoidal signal of positive polarity 100Hz, amplitude approximately 4.5V, with the SignalTap II logic analyzer
Analyzed the conversion result.
c) achieve a single AD conversion: Each time you press the button, and automatically generates a set of CS clock to complete a conversion, the conversion result
Results are displayed on digital. (2014-03-26, VHDL, 328KB, 下载3次)
ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。
在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信）
ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from the control on the temperature, humidity, photoresistors, thermistors, and other information (including the main control machine from the control machine by zigbee protocol communications) (2012-05-18, VHDL, 1356KB, 下载23次)
微型打印机模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。
在quartusII里面添加uart核，nios II的Console构成人机交互界面，串口与微型打印机通信，打印出数据。
Micro printer module experiment rar core on the FPGA-2C35 Borch experimental box platform. QuartusII inside to add the uart nuclear, nios II Console constitute a man-machine interface, serial ports, and micro-printer communications, print out the data. (2012-05-18, VHDL, 12837KB, 下载8次)
以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字
滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了
对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结
果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求
W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has
developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is
show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on
FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design
requirement . (2011-04-20, VHDL, 15KB, 下载62次)
基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码输入错误时，LED灯D8亮，并在LCD显示屏上显示字符串“NO!!You stupid!!you are worry!!!”其中，LCD显示作为本次设计的核心内容，字符型LCD通常有14条引脚线或16条引脚线的LCD，多出来的2条线是背光电源线VCC(15脚)和地线GND(16脚)，其控制原理与14脚的LCD完全一样
Base YuBo gen experiment box UP- FPGA2C35- Ⅱ and director- Verilog HDL hardware description language, divided into key input module, the LED indicator light module and LCD display module, the BTN1, BTN2 buttons as input the input password and set in four matches, the password by D1, D2 and D3, D4 four lamp that LED lamp to indicate input password of digits. Boot, LCD display "HELLO!!!!!!!!!! The code: backgound Enter when", a password when right, LED lamp, while D7 light displayed on the LCD screen experiment box string "Good!! Well done! You right!!!" hero When a password mistake, LED lamp light, and in D8 displayed on the LCD screen "NO!! You string can be hindered stupid!!!!!!!!!!!!!!!!!" hero Among them, LCD display as the core content of the design, character type LCD usually has 14 pin line or 16 pins line of LCD, extra 2 line is backlit cord VCC (15 feet) and landlines GND (16 feet), the control principle and 14 feet LCD exactly the same
(2011-04-10, TEXT, 3KB, 下载16次)
高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。
):
1统控制的电梯往返于1-9层楼。
2客要去的楼层数可手动输入并显示（设为A数）。
3梯运行的楼层数可自动显示（设为B数）。
4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；
当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；
当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门；
5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。
注：此为word文档，但里面有源代码。
High-rise elevator control system (Windows platform programming software running on the ispLEVER.
):
An elevator control system and from 1-9 floors.
2, the number of passengers going to the floor can manually enter and display (Make A number).
3 ladder run automatically display the number of floors (Set B number).
4A> B, the system can output three-phase motor is transferred to the timing signal to lift up
When A <B, the system can output three-phase motor to reverse the timing signal to the lift down
When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door
5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch.
Note: This is a word document, but inside the source code. (2010-06-10, VHDL, 34KB, 下载19次)
数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成
果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用
并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。
NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems. (2009-04-11, VHDL, 170KB, 下载42次)
是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除
Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division (2009-03-17, VHDL, 18KB, 下载45次)
verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，
Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off, (2007-09-09, Others, 2512KB, 下载177次)