[VHDL/FPGA/Verilog] 抢答器
能准确判断出抢答者的电器。在知识竞赛、文体娱乐活动（抢答赛活动）中，能准确、公正、直观地判断出抢答者的座位号。更好的促进各个团体的竞争意识，让选手门体验到战场般的压力感。
Can accurately determine the electrical appliances of the responder. In knowledge contest, recreational and sports activities (contest activities), the seat number of the responder can be accurately, fairly and intuitively determined. Better promote the competition awareness of all groups, and let the competitors experience the battlefield like pressure. (2020-03-14, C/C++, 12KB, 下载0次)
[VHDL/FPGA/Verilog] FSK
产生15位的伪随机序列作为调制信号信源，采用频率选择法实现2FSK调制，采用鉴频法实现2FSK解调，可以仿真实现，也可使用示波器观测调制、解调信号。
A 15 bit pseudo-random sequence is generated as the source of the modulation signal. The 2FSK modulation is realized by the frequency selection method and the 2FSK demodulation is realized by the frequency discrimination method. It can be realized by simulation or by using an oscilloscope to observe the modulation and demodulation signals (2020-01-08, Verilog, 8676KB, 下载3次)
[VHDL/FPGA/Verilog] verilog
用fpga制作一个音乐播放器，此为浙江大学信电系fpga教程大实验成果。
Use fpga make a music player, this is the letter Electrical Zhejiang University fpga tutorial big experiment results. (2016-11-08, VHDL, 35648KB, 下载78次)
[VHDL/FPGA/Verilog] RGMII
用xilinx芯片实现千兆网的实例代码，您可以通过修改此代码完成基于ETMAC IP核的MAC设计，驱动外部PHY芯片或进行MAC to MAC 的直连通信设计。
this is code of etmac IP inst.. it will help you developing for MAC and PHY (2016-04-16, VHDL, 96KB, 下载105次)
[VHDL/FPGA/Verilog] ddrpspsbf
基于FPGA的雷达脉冲预分选器设计--这里, 提出一种基于关联比较器的雷达信
号分选方法,在实现多参数分选的同时, 也保证了实时性。详细阐述了在 Virtex 4 系列 FPGA 上实现基于内容可寻存储器
( CAM)的关联比较器的途径。
Design of Radar Pulse Signal Pre-sorting Based on FPGA (2014-06-03, VHDL, 346KB, 下载13次)
[VHDL/FPGA/Verilog] MSK
FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页
MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247 (2014-04-09, VHDL, 1690KB, 下载69次)
[VHDL/FPGA/Verilog] eetop.cn_VHDL1-
VHDL 实用教程
本书比较系统地介绍了VHDL 的基本语言现象和实用技术全书以实用和可操作为基点简洁而又不失完整地介绍了VHDL 基于EDA 技术的理论与实践方面的知识
VHDL practical tutorial book systematically introduces the basic phenomenon of VHDL language and practical skills book with practical and workable starting point is simple and yet complete introduction to the theory and practice of VHDL-based EDA technology knowledge (2013-12-09, VHDL, 2839KB, 下载2次)
[VHDL/FPGA/Verilog] DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。
Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output. (2013-07-25, matlab, 3KB, 下载119次)
[VHDL/FPGA/Verilog] eetop.cn_emif_brg
fpga与DSP通过emif接口通信，fpga内部通过fifo进行数据缓存
fpga with the DSP through emif interface communication, fpga internal data cache by fifo (2013-03-16, VHDL, 4KB, 下载41次)
[VHDL/FPGA/Verilog] clock
时钟分配电路，输入为时钟信号CLK，输出为信号F0~F5，这六个信
号中只允许有一个为高电平，F0、F2、F4的持续时间为2个CLK，F1、F3、F5的持续时间为4个CLK。
A clock distribution circuit, the input clock signal CLK, the output signal F0 ~~ F5, the six signal only allowed to have a high level, F0, F2, F4 duration of two CLK, F1, F3, F5 duration of four CLK. (2012-12-03, VHDL, 1KB, 下载17次)
[VHDL/FPGA/Verilog] Sender
直序扩频通信发送部分的源代码，用verilog编的，包括信源模块、扩频模块、极性变换模块和DDS调制模块
Direct sequence spread spectrum communication sent part of the source code, compiled with verilog source modules, spread spectrum modules, polarity transform module and DDS modulation module (2012-11-05, VHDL, 13566KB, 下载51次)
[VHDL/FPGA/Verilog] BasysRevEBist
basys板描述介绍信号发生器在科研以及生产实践领域有着广泛的应用。传统的信号发生器通常是通过
模拟电路的振荡、变换得到各种信号。由于模拟器件以及模拟电路自身的局限性，其发展已
经遇到了瓶颈。直接数字
kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.This design can make adjustable sine,triangle and rectangle waveform.It also can show the waveform real time on a computer dispaly or a projecting apparatus via (2012-06-16, VHDL, 1221KB, 下载5次)
[VHDL/FPGA/Verilog] eetop.cn_fft
采用全流水线结构，供初学者参考，附有仿真波形图，代码中上有可以改进之处，如蝶形单元中可以将4次乘法简化为3次乘法，不过要预先对旋转因子做处理，第一次上传，如有不妥之处，还请大家指正，谢谢。
With full pipeline structure, reference for beginners, with a simulation waveform diagram, the code can be on improvements, such as the butterfly unit can be reduced to 4 times 3 times multiplication multiplication, but to do pre-processing of the rotation factor, first upload, if inappropriate, but also please correct me, thank you. (2011-08-09, VHDL, 44KB, 下载11次)
[VHDL/FPGA/Verilog] PWM256
Verilog 所寫的可程式 PWM 信號產生器. 特點是設定參數時不會產生Glitch現象. 包含二個 .do 檔給 model*sim 幫助編譯及模擬.
A PWM generator writing in Verilog. This module will generate glitch while changing the setting. Including 2 .do files which can help compiling and simulating in the model_sim. (2011-04-18, Others, 2KB, 下载17次)
[VHDL/FPGA/Verilog] communications_2
用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或），crc解码，数据串行输出。
Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m sequence generated sparse 1, then the encoded data and XOR), crc decoding, serial output data. (2010-08-27, VHDL, 118KB, 下载30次)
[VHDL/FPGA/Verilog] communications_1
用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。
Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m sequence generated sparse 1, then the encoded data and XOR). (2010-08-27, VHDL, 472KB, 下载14次)
[VHDL/FPGA/Verilog] sy2
晶振频率为4.096MHz，系统同步时钟为256KHz，每个时隙占8位；
四路支路信码各为8位，分别为：
1 1 1 0 0 1 0 1 ；1 1 0 1 1 0 0 1 ；1 0 0 1 1 1 0 1 ；
1 1 1 0 1 0 1 1 ；
复接方式采用：按位同步复接。
library IEEE
use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all
(2010-04-16, VHDL, 182KB, 下载24次)
[VHDL/FPGA/Verilog] Transmitter
该程序是整个OFDM发射机的程序，希望对做这方面的朋友用些帮助，也希望朋友们和我一起探讨OFDM收发信机。
The program is the whole OFDM transmitter of the program, want to do this in a friend with some help, I hope my friends join me to explore OFDM transceiver. (2010-01-03, VHDL, 2583KB, 下载63次)
[VHDL/FPGA/Verilog] baseonFPGA
实时电话计费系统是企业、事业单位信息管理的一个重要组成部分。介绍了一种用FPGA 器件实现电话计费系统
的方法, 并给出了设计框图和详细设计过程, 设计采用Verilog_HDL 硬件语言。
Real-time telephone billing system is the enterprise information management institutions as an important component. Introduction of a FPGA device using telephone billing system methods, and gives the design diagram and detailed design process, design hardware Verilog_HDL language. (2008-07-11, VHDL, 519KB, 下载70次)
[VHDL/FPGA/Verilog] calculator
用VHDL编写的计算器，能实现简单的加减乘除四则运算 (2007-08-28, Others, 21KB, 下载108次)
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