[VHDL/FPGA/Verilog] eetop.cn_利用FPGA实现浮点运算的verilog代码
计算机里整数和小数形式就是按普通格式进行存储，例如1024、3.1415926等等，这个没什么特点，但是这样的数精度不高，表达也不够全面，为了能够有一种数的通用表示法，就发明了浮点数。
浮点数的表示形式有点像科学计数法（*.*****×10^***），它的表示形式是0.*****×10^***，在计算机中的形式为 .***** e ±***），其中前面的星号代表定点小数，也就是整数部分为0的纯小数，后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数，例如1024就能表示成0.1024×10^4，也就是 .1024e+004，3.1415926就能表示成0.31415926×10^1，也就是 .31415926e+001，这就是浮点数。浮点数进行的运算就是浮点运算。
浮点运算比常规运算更复杂，因此计算机进行浮点运算速度要比进行常规运算慢得多。
Floating point representation is a bit like scientific notation (*.***** * 10^***), its representation is 0.***** * 10^*** in the computer in the form of.***** e +, * * *) in front of the asterisk represents fixed-point decimal, which is part of the 0 pure decimal integer index, part of the back is a fixed integer. In this way, any integer and decimal can be expressed. For example, 1024 can be expressed as 0.1024 * 10^4, that is,.1024e+004, 3.1415926 can be expressed as 0.31415926 * 10^1, that is.31415926e+001, that is the floating point number. The operation of floating-point numbers is floating point operation. (2018-03-12, Quartus II, 127KB, 下载24次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步
The module' s function is to verify the basic realization and PC serial communication functions. Required on the PC to install a serial debugging tools to verify functionality of the program. Program implements a transceiver a 10 bit (ie, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law by the parameters defined in the program div_par decision to change the parameters of the corresponding baud rate can be achieved. Program is currently set div_par value is 0x104, corresponding to the baud rate is 9600. 8 times the baud rate with a transmit or receive clock cycle time of each bit is divided into eight time slots to the communication sync (2013-07-02, VHDL, 346KB, 下载1次)
[VHDL/FPGA/Verilog] modulation-realise
用Matlab产生一个频率为1Hz、功率为1的余弦信源，设载波频率为10Hz，并画出：
1.DSB调制信号及其功率谱密度；
2.将已调信号解调，在时域内将解调后的波形与原信号进行对比；
3.A=2的AM调制信号及其功率谱密度；
4.SSB调制信号及其功率谱密度；
5.在信道中各自加入经过带通滤波器后的窄带高斯白噪声，功率为0.1，解调各个信号，并画出解调后的波形。
Matlab produce a frequency for 1 hz, power for 1 cosine source, a carrier frequency for 10 hz and draw the:
1. The DSB modulation signal and power spectral density
2. Will be modulated signal demodulation, in the time domain waveform and the demodulation of the original signal are compared
3. A = 2 AM modulation signal and power spectral density
4. SSB modulation signal and power spectral density
5. In the channel of each join after bandpass filter after the narrow band gaussian white noise, power is 0.1, each signal demodulation, and draw the demodulation of waveform.
(2012-12-04, matlab, 19KB, 下载77次)
[VHDL/FPGA/Verilog] fpxz
分频选择系统。inclk0端输入25MHz信号，通过altpll倍频为400MHz信号C0端输出，需求不一样自己改倍频器参数。分频器clkdiv用来二分频、四分频、八分频、十六分频，分别分频为200MHz、100MHz、50MHz、25MHz四种频率信号输入到选择器中。选择器的TCLK是外部输入信号，A[3..0]是四个独立按键，选择器是用按键的不同组合来从四个分频喜好和一个TCLK中选择一路输出。代码清晰易懂，不符合需求请自行扩展
Frequency selection system. the inclk0 side input 25MHz signal, multiplier by altpll at 400MHz signal C0-ended output, demand not the same as their own to change the parameters of frequency multiplier. The divider clkdiv used divided by two, divide-eighth of the frequency, and 16 divided by, respectively, are at a frequency of 200MHz, 100MHz, 50MHz, 25MHz four kinds of frequency signals input to the selector. Select the TCLK is an external input signal, A [3 .. 0] four separate buttons, selector all the way to the output with a different combination of buttons to choose from the four sub-frequency preferences and TCLK. Code is clear and easy to understand, does not meet the needs of your own expansion (2012-05-17, VHDL, 339KB, 下载12次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
The function of this module is to verify the basic serial communication and PC. Need to be installed on a PC with a serial debugging tools to verify the functionality of the program.
The program implements a send and receive a 10-bit (ie, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit.
The serial port s baud law determined by the procedures defined in div_par parameters, change the parameters to achieve the appropriate baud rate. The value of the procedures set div_par
0x145, corresponding to the baud rate is 9600. An eight times the baud rate clock to send or receive every bit of the cycle time is divided into eight time slots so that through
Letter synchronization. (2012-03-05, Windows_Unix, 55KB, 下载2次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
The module' s function is to verify the implementation and the PC for basic serial communication functions. Installed on a PC requires a serial port debugging tool to verify the functionality of the program. Program implements a send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud law by the parameters defined in the program div_par decision to change the parameters of the corresponding baud rate can be achieved. The program is currently set div_par value 0x145, corresponding to the baud rate is 9600. 8 times the baud rate with a clock to send or receive every bit of the cycle time is divided into eight time slots so that the communication synchronization. (2011-06-22, VHDL, 349KB, 下载3次)
[VHDL/FPGA/Verilog] qpsk_demod_use_FPGA
根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点，符合未来通信技术发展的方向。
According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development. (2010-12-06, Windows_Unix, 63KB, 下载42次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
程序的基本工作过程是，按动一个按键SW0，控制器向PC的串口发送“welcome"，
PC机接收后显示验证数据是否正确（串口调试工具设成按ASCII码接受方式）.
PC可随时向CPLD发送0-F的十六进制数据，CPLD接受后显示在7段数码管上.
The module s function is to verify the implementation and the basic PC, the serial communication function. Need PC,
Install a serial debugging tools to verify the functionality of the program.
Program implements a receive a 10 bit (ie no parity bit) of the serial controllers, 10
bit is a start bit, 8 data bits, 1 stop bit.
Serial Porter law defined by the program parameters div_par decision can change the parameters of the corresponding
Baud rate. Program the value of the current set div_par
Is 0x104, the corresponding baud rate is 9600. 8 times the baud rate with a clock will be sent or received per
A bit of the cycle time is divided into eight time slots in order to pass
Information synchronization.
The basic process is the work program, press a button SW0, the controller s serial port to the PC
"Welcome",
PC, after receiving the authentication data displayed is correct (serial debugging tool ASCII code set by the r (2010-11-28, VHDL, 2KB, 下载10次)
[VHDL/FPGA/Verilog] DMX512_2_23
本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡，它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件，可以控制电脑灯或者其他DMX512协议的设备，比如LED灯、激光灯、PAR灯、DJ设备等等。
本系统还有体积小巧携带方便等特点，足够一般的娱乐场所、多功能厅、会议厅等场所使用，同时采用电脑进行灯光的控制，也可以提升工程的技术含量，显得更高科技。通过简单更改DMX模块的UART部分，还可以将串口转换usb接口，不过由于手头上的FPGA开发板没有USB接口，所以使用UART接口进行测试。
The system design using FPGA, a serial port on the computer then a DMX512 protocol adapter, it can make your computer into a super computer console or lighting console lights, LED controller. Through computer software, can control lights or other DMX512 protocol computer equipment, such as LED lights, laser lights, PAR lamps, DJ equipment. The system also features compact, portable and so on, is sufficient for most of the entertainment, function rooms, conference rooms and other places to use, while using computer control of lighting can also enhance the project s technical content, appears to higher technology. DMX module by simply changing the UART portion can also convert usb serial interface, however, because the FPGA development board on hand no USB interface, so tests using the UART interface.
(2010-07-11, VHDL, 2171KB, 下载270次)
[VHDL/FPGA/Verilog] Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a
本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础
上，采用超高速集成电路硬件描述语言(VeryHighspeedxntegatedeireuitHardware
DescriptionLan即age，简称VHDL)在Altera公司 Quartusll7.0开发环境下设计并实现各个功能块，通过仿真来证明功能正确性。再次，用 Protel99SE进行印制电路板(Prinicircuitboard，简称PcB)设计，从原理图到封装，再到布局布线。焊接调试完毕后，将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbPs，调制中频10MHz。测试结果验证系统的正确性，实现了从数字基带到中频的可4一DQPSK调制解调系统
This study is the first 4 1 DQPsK modem modulation system, part of the basic principles and design of each module, focusing on shaping filter and a direct digital frequency synthesizer (DireetoigitalFrequeneySynihesis, referred to as DDS), and to address all the key modules algorithm matlab design simulation to show simulation results. Second, the study of modulation and demodulation system demodulation part of the basic principles and design of each module, focusing on differential demodulation, digital down conversion and bit synchronization algorithm, but also for its various key module of the Matlab algorithm design and simulation. Then use the Matlab simulation of the entire system theory, reach a conclusion. On this basis,
, Using ultra-high speed integrated circuit hardware description language (VeryHighspeedxntegatedeireuitHardware
DescriptionLan that age, referred to as VHDL) in the Altera Corporation Quartusll7.0 development environment to design and implement the variou (2010-02-03, VHDL, 5330KB, 下载94次)
[VHDL/FPGA/Verilog] myprojects
同步数字复接的设计及其FPGA实现
在简要介绍同步数字复接基本原理的基础上，采用VHDL语言对同步数字复接各组成模块进行了设计，并在ISE集成环境下进行了设计描述、综合、布局布线及时序仿真，取得了正确的设计结果，同时利用中小容量的FPGA实现了同步数字复接功能。
基群速率数字信号的合成设备和分接设备是电信网络中使用较多的关键设备，在数字程控交换机的用户模块、小灵通基站控制器和集团电话中都需要使用这种同步数字复接设备。近年来，随着需要自建内部通信系统的公司和企业不断增多，同步数字复接设备的使用需求也在增加。FPGA(现场可编程门阵列)器件的高性能简化了数字通信系统的设计与实现。本文基于FPGA的技术特点，结合数字复接技术的基本原理，实现了基群速率(2048kbps)数字信号的数字分接与复接。
VHDL (2009-04-30, VHDL, 2342KB, 下载95次)