中文版 Parallel Programming for FPGAs
Chinese version of Parallel Programming for FPGAs (2022-09-30, CSS, 13691KB, 下载0次)
基于wishbone总线的SPI主设备代码
spi master based on wishbone bus (2018-05-02, Verilog, 242KB, 下载2次)
用Verilog编写的带FOFI的UART model,比较好
FOFIUART model wrote by Verilog coding (2017-11-24, Verilog, 171KB, 下载5次)
通用的GPIO coding,Verilog编码
GPIO coding wrote by Verilog (2017-11-24, Verilog, 9KB, 下载4次)
异步FIFO的Verilog程序及其测试程序
FPGA/Verilog FIFO_ASYN (2017-09-14, Verilog, 67KB, 下载5次)
SystemVerilog设计(第二版) 用于编写TESTBENCH;
eetop.cn_SystemVerilog for Design(Second Edition) (2015-09-18, Unix_Linux, 2310KB, 下载8次)
uart接收模块,Vrilog编写,实现与PC机的同信
UART Receiver module (2014-11-04, VHDL, 2KB, 下载1次)
cpu查询工具
look for cup look for cup look for cup (2014-03-07, Visual C++, 930KB, 下载2次)
实 时 信 号 处 理 的 VHDL 代 码
VHDL code for real-time signal processing (2012-08-27, VHDL, 1588KB, 下载4次)
TCD1209D 时序驱动采用VHDL语言
TCD1209 drive (2012-05-20, VHDL, 1KB, 下载53次)
ARM汇编指令集详解,包括ARM7架构和大部分汇编指令,宛城布衣整理
ARM instruction set Detailed assembly, finishing Wancheng commoner (2010-12-21, VHDL, 968KB, 下载9次)
简单的VGA veliog fpga 测试小程序,显示彩条
a simple vga verilog fgpa test (2010-12-09, Unix_Linux, 40KB, 下载4次)
一个模拟视频输入转VGA视频输出的Verilog程序,经过验证
vga verilog code,already pass (2010-12-09, Unix_Linux, 529KB, 下载4次)
信噪比可变的加性高斯白噪声信道下信号发生器的VHDL语言编程实现
the realization of data-creater on AWGN channel (2010-10-14, VHDL, 68KB, 下载235次)
Modelsim教程,从事FPGA等开发入门的教材
Modelsim tutorial engaged FPGA etc. development entry materials (2010-04-07, VHDL, 515KB, 下载17次)
很好的quartus软件仿真教程,flash版。
Good quartus software simulation tutorials, flash version. (2009-09-14, VHDL, 15552KB, 下载22次)
Answers for Chapter 1 to 5 of The C Programming Language (KnR)
Answers for Chapter 1 to 5 of The C Programming Language (KnR) (2009-06-01, C/C++, 42KB, 下载3次)
Altera的40-nm收发器系列产品, 发展趋势和挑战
Altera的40-nm收发器系列产品, 发展趋势和挑战 (2009-05-04, PDF, 985KB, 下载2次)
很好的一本关于verilog的中文教程!
Very good one on the Chinese Verilog Tutorial! (2008-06-10, PDF, 2859KB, 下载8次)
波形发生器,带TESTBENCH,
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn (2006-08-19, MultiPlatform, 1KB, 下载37次)