SystemVerilog for Verification A Guide to Learning the Testbench Language Features Third Edition中文翻译,
SystemVerilog for Verification A Guide to Learning the Testbench Language Features Third Edition, (2022-01-10, Others, 0KB, 下载0次)
FPGA电子琴，用代码实现琴的功能，挺有意思的。可供学学娱乐
FPGA electronic piano, with code to achieve the function of the piano, very interesting. For learning and entertainment (2020-04-29, C/C++, 1006KB, 下载0次)
DDR的控制器啦啦信不信由你非常实用又实用的历程哈
DDR MIG IT is my favorite pdf and FPGA projects yes you are right (2019-05-29, VHDL, 3214KB, 下载0次)
实现串口一转四通信，补偿系数片内存储修正功能
Implementing Serial Port One to Four Communication, Compensation Coefficient Memory Correction Function (2019-01-06, Verilog, 1109KB, 下载0次)
基2方法实现的8点fft，可以用于对fft的学习。
FFT 8 point implementation, the implementation of the base 2 algorithm, FPGA verification function. (2018-08-14, VHDL, 479KB, 下载0次)
ISCAS89测试基准电路，verilog编写，可用于测试向量的生成
iscas89 benchmark, written in verilog language, can be used to generate test pattern (2018-08-13, VHDL, 1010KB, 下载5次)
无线通信FPGA源代码，供大家使用啊啊啊啊
wuxiantongxinFPGA VERILOG HDL (2017-07-06, VHDL, 196KB, 下载6次)
powerlink主从站代码，基于x86/arm/fpga，分别都有例程
powerlink mn/cn code，base on x86/arm/fpga (2016-09-08, C/C++, 5678KB, 下载67次)
为随机序列产生器，可以作为调制信号的信源
As the random sequence generator, can be used as a modulation signal source (2016-04-09, VHDL, 1KB, 下载2次)
实现usb的通信，实现计算机和FPGA之间的同信
Realization of USB communication (2013-05-10, VHDL, 2KB, 下载4次)
基于fpga产生的伪随机数，很好的学习资料，值得学习
Fpga generate pseudo-random numbers, good learning materials, it is worth learning (2012-09-27, PHP, 104KB, 下载3次)
飞利浦出的英文版的fpga设计，英文好的可以看看。
The Philips out the English version of the fpga design, English can look good. (2012-09-03, Others, 3346KB, 下载6次)
74AC163可编程计数器用作分频精度高速度快
The 74AC163 programmable counters used for frequency accuracy of high-speed fast (2012-07-24, Visual C++, 89KB, 下载2次)
Modelsim 6.6c keygen
Modelsim 6.6c keygen (2011-01-26, VHDL, 652KB, 下载190次)
电路设计和仿真工具hspice的重要使用文档。无师自通
Circuit design and simulation tools hspice important use of documents. Without a teacher (2010-07-04, VHDL, 1237KB, 下载1次)
QuartusII6.0简体中文教程.pdf，讲的很详细，共有260页，很好的资料
QuartusII6.0 English tutorial. Pdf, said very detailed, 260 pages, very good information (2010-04-04, PDF, 2020KB, 下载4次)
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
(2009-04-27, VHDL, 4KB, 下载11次)
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn (2006-08-19, MultiPlatform, 2KB, 下载75次)
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
-- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn (2006-08-19, MultiPlatform, 1KB, 下载5次)