集成电路设计大赛ARM杯作品,获得2021年ARM企业杯,
The works of ARM Cup in the integrated circuit design competition won the ARM Enterprise Cup in 2021, (2021-09-26, VHDL, 0KB, 下载0次)
设计时钟分频电路，使输出的时钟信号具有不同的占空比，用时钟信 号驱动LED，从而实现LED亮度的调节。使用按键开关调节LED亮度 ，至少实现LED亮度5级可调。 (2022-04-25, VHDL, 998KB, 下载0次)
http://www.pudn.com/Download/item/id/1650855600652838.html
数字ic面试题目以及一些面试的经验，帮助ic设计工作者找到人生中的第一份工作
Digital IC interview (2017-10-19, VHDL, 41KB, 下载12次)
根据vhdl设计的32位CPU具备加减 读写等标准功能
a 32-bit cpu based on VHDL designed with function of fundamental function of subtraction , addition, load and store . (2017-07-16, VHDL, 19KB, 下载2次)
Xilinx的Convolution Encode v6.1手册的中文版，本人翻译。可作为快速学习卷积码编码资料。
The Xilinx Convolutional Encoder v6.1 manual Chinese version, my translation. Learn as fast convolution code information. (2015-12-30, VHDL, 161KB, 下载2次)
浮点运算单元进行加减乘除运算，进行64位双精度浮点运算。
Floating-point arithmetic operations unit, double-precision 64-bit floating-point arithmetic (2014-05-29, VHDL, 364KB, 下载5次)
eetop.cn_Verilog编写的M序列发生器,//产生M序列的发送信号indata(随机),并且将接收到的解码信号（decode）进行比较。发送的头10个信号为1，第11个为0，在解码的开始时期进行同步判断时用到。
prepared by the M-sequence generator eetop.cn_Verilog / / M sequences generated transmission signal indata (random), and decodes the received signal (decode) for comparison. The first 10 to send a signal to the first 11 to 0, the decoding start time is used to synchronize the judgment. (2013-10-25, VHDL, 5KB, 下载18次)
axi总线读写通道插入一级寄存器模块verilog源码,已验证...
a slave interface is simple to achieve, need to look at (2013-04-10, VHDL, 2KB, 下载21次)
光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信
号
光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信
号 (2011-11-30, VHDL, 1KB, 下载21次)
EE224 Sjsu exam material
EE224 Sjsu exam material (2011-03-04, VHDL, 9763KB, 下载1次)
美信onewire总线IP core,带验证激励
MAXIM DS1WM
Synthesizable 1-Wire Bus Master IP core. (2010-12-10, VHDL, 55KB, 下载54次)
这个是分布式基站BBU和RRU的IR接口的接口芯片Datasheet
This is a distributed base station BBU and RRU' s IR interface interface chip Datasheet (2010-09-13, VHDL, 40KB, 下载8次)
该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。
The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules. (2010-06-27, VHDL, 6KB, 下载46次)
用于SD卡通信控制部分的命令收发部分，verilog语言描述
Communications control part for the SD card send and receive part of the command, verilog language to describe the (2009-12-08, VHDL, 7KB, 下载12次)
ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture
AMBA ）规范中文版，包括ASB，AHB，APB总线
Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus (2009-08-23, VHDL, 1052KB, 下载206次)
-- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
-- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
(2009-04-27, VHDL, 4KB, 下载71次)
cpld 控制 8-32M sdram 控制器 maxII epm570实现。
pdf 的说明文件
CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation (2008-09-04, VHDL, 188KB, 下载94次)
nios调试过程中发生的错误信息总结~~~
源文件有密码~~文件名就是密码~
Debugging Nios occurred during the summing up of the error message source files ~ ~ ~ ~ ~ Have a password file name is the password ~ (2008-08-28, VHDL, 295KB, 下载16次)
NIOS_II，开发文档，中文描述，比较适合于新手，可以帮助了解NIOS开发全过程。
NIOS_II, development documents, the Chinese description, suitable for novice, can help to understand the development of the whole process of NIOS. (2008-07-09, VHDL, 974KB, 下载8次)
.net 3。2 企业级分布式项目案例，应用wcf技术
. net 3. 2 enterprise-class distributed project case, the application WCF technology (2008-05-14, VHDL, 7120KB, 下载139次)