基于FPGA的数字调制系统 :实现m序列作为信源,并通过按键来选择移位相加的初始值和步进值以及实现2ASK、2FSK、2PSK
FPGA based digital modulation system: implementing m sequence as the signal source and selecting the initial and step values of shift addition through buttons, as well as implementing 2ASK, 2FSK, 2PSK (2021-06-04, Verilog, 48KB, 下载0次)
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
A comprehensive Chinese tutorial on Bluespec SystemVerilog (BSV), introducing advanced features such as BSV scheduling, FIFO data flow, and polymorphism, showcasing the advantages of BSV compared to traditional Verilog development. (2023-03-28, Bluespec, 30674KB, 下载0次)
tes dst 的D/AVE 3d加速核心
D/AVE 3D是3D图形应用的经济高效的IP核心。该核心可用于FPGA、ASIC和SOC，专门为嵌入式、汽车和信息娱乐市场设计，重点强调硬件和软件的灵活性。
D/AVE 3D is cost-efficient IP core for 3D graphics applications. This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software. (2019-04-08, VHDL, 36829KB, 下载0次)
企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。
Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files. (2015-05-31, VHDL, 2074KB, 下载4次)
根据小波去噪的原理及特点，提出了用FPGA实现小波实时信号处理的方法。实验结果证明采用FPGA实现小波信号处理能在低信噪比的情况下有效去除噪声，同时能够满足信号处理系统的实时性要求。
According to the principles and characteristics of wavelet denoising, a method using wavelet FPGA real-time signal processing. Experimental results show that using FPGA wavelet signal processing at low signal to noise ratio can effectively remove noise while being able to meet the requirements of real-time signal processing system. (2015-02-28, VHDL, 503KB, 下载29次)
语音信箱控制模拟语音信箱收信、发信、存信、擦除信息等，允许用户发送信息、重阅信息、存储信息和擦除信息
Voicemail controlled analog voice mail reception, letter, Cunxin, erase information, allowing users to send messages, re-read the information, store information and erase information (2013-07-12, VHDL, 3KB, 下载2次)
大型电玩城碎票机主板的源程序。涉及到UCN5821+数码管（程序中子函数为wr595,与74hc595略有不同）的运用、stc11系列eeprom的运用，内附原理图，可以根据一个具体小项目入门结构化设计。KILL 4打开。
City broken ticket machine arcade board of the source. Involves UCN5821+ digital tube (Functions of program wr595, with 74hc595 slightly different) the use, stc11 series eeprom use, containing schematics, according to a specific structural design small project started. KILL 4 opens. (2013-07-04, C/C++, 89KB, 下载5次)
OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图
Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure (2013-06-05, matlab, 4KB, 下载143次)
采用Xilinx的Sysgen工具建立的16QAM调制制解调模型，其中包括信源生成、多普勒频偏、载波跟踪环路等。
16QAM modulation using Xilinx Sysgen tool to establish the modem model, including source to generate the Doppler shift, the carrier tracking loop. (2012-07-26, Visual C++, 29KB, 下载9次)
MAX481、MAX483、MAX485、MAX487-MAX491以及
MAX1487是用于RS-485与RS-422通信的低功耗收发器，
每个器件中都具有一个驱动器和一个接收器
The MAX481, MAX483, MAX485 The MAX487-MAX491, and MAX1487 low-power transceivers for RS-485 and RS-422 communication, each device has a drive and a receiver (2012-07-10, PDF, 738KB, 下载10次)
本程序源码为通信系统中的GMSK调制程序源码，对于研究通通信调制解调的人来说十分有用！ 可直接使用。 已通过测试。
The program source code for GMSK modulation communication systems program source code, very useful for the study through communication modem Can be used directly. Has been tested. (2012-06-28, matlab, 20KB, 下载8次)
1 采用正弦波，方波进行同步调制，实现调制信号、已调信号、解调信号的波形、频谱以及解调器输入输出信噪比的关系。
2 采用Verilog语言编写有符号的五位乘法器
3 实现数字与模拟调制
A sine wave, square wave synchronous modulation to achieve the modulation signal, the modulated signal, the demodulated signal waveform, spectrum and signal to noise ratio of the demodulator input and output relationship. 2 using Verilog language has signed five digital and analog multiplier 3 modulation (2011-11-10, matlab, 546KB, 下载60次)
this is the license genarator for xilinx ISE DESIGN SUIT 13.1
this is the license genarator for xilinx ISE DESIGN SUIT 13.1 (2011-10-04, VHDL, 286KB, 下载92次)
采用Verilog在FPGA上实现一阶Σ-Δ DAC，仿真和实际验证都正确，基本可以达到16位DAC的信噪比
Using Verilog to implement the first sigma delta DAC on the FPGA, the simulation and practical verification are correct, basically can achieve 16 bit DAC signal-to-noise ratio (2010-04-08, VHDL, 15KB, 下载35次)
实现一个加/减8进制计数器。其中包括时钟输入、使能信号、加减控制信
号、复位信号、三位输入和一位进位位。
To achieve a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit. (2009-09-02, VHDL, 32KB, 下载24次)
verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。
verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence. (2009-07-29, VHDL, 10308KB, 下载383次)
在信威dsp软件面试、汉王笔试、扬智电子笔试、新太硬件面题时的题目
Xinwei dsp software in the interviews, written Hanwang, ALi electronic written, the new hardware side too, when the topic title (2009-07-27, TEXT, 2KB, 下载24次)
quartusii8.0正式版破解器,正式版可到官网去下载。http://www.altera.com.cn/
quartusii8.0_crack (2009-02-03, VHDL, 15KB, 下载48次)
使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为-10DB
CDMA system using MATLAB to complete the relevant receivers, which Hadamard matrix of 128 bands, simulation-10DB-bit signal to noise ratio for (2008-08-06, matlab, 1KB, 下载43次)
真序扩频通信系统的SYSTEMVIEW信真及其FPGA实现发送端设计
True sequence spread spectrum communication system SYSTEMVIEW letter really realize the sending end and FPGA design (2007-09-21, Others, 1465KB, 下载32次)