[VHDL/FPGA/Verilog] EP1C3-uart_1_verilog
EP1C3-uart_1_verilog,程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
EP1C3-uart 1 verilog, implements a program to send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit.
Baud-law decided by div_par parameters defined in the program, you can change the parameters to achieve the appropriate baud rate. Value of the program is currently set div_par
Is 0x145, the corresponding baud rate is 9600. An 8 times the baud rate clock to send or receive every bit of the time period is divided into eight time slots so that the pass
Letter synchronization. (2016-03-09, VHDL, 334KB, 下载2次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步
The module' s function is to verify the basic realization and PC serial communication functions. Required on the PC to install a serial debugging tools to verify functionality of the program. Program implements a transceiver a 10 bit (ie, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law by the parameters defined in the program div_par decision to change the parameters of the corresponding baud rate can be achieved. Program is currently set div_par value is 0x104, corresponding to the baud rate is 9600. 8 times the baud rate with a transmit or receive clock cycle time of each bit is divided into eight time slots to the communication sync (2013-07-02, VHDL, 346KB, 下载1次)
[VHDL/FPGA/Verilog] fpxz
分频选择系统。inclk0端输入25MHz信号，通过altpll倍频为400MHz信号C0端输出，需求不一样自己改倍频器参数。分频器clkdiv用来二分频、四分频、八分频、十六分频，分别分频为200MHz、100MHz、50MHz、25MHz四种频率信号输入到选择器中。选择器的TCLK是外部输入信号，A[3..0]是四个独立按键，选择器是用按键的不同组合来从四个分频喜好和一个TCLK中选择一路输出。代码清晰易懂，不符合需求请自行扩展
Frequency selection system. the inclk0 side input 25MHz signal, multiplier by altpll at 400MHz signal C0-ended output, demand not the same as their own to change the parameters of frequency multiplier. The divider clkdiv used divided by two, divide-eighth of the frequency, and 16 divided by, respectively, are at a frequency of 200MHz, 100MHz, 50MHz, 25MHz four kinds of frequency signals input to the selector. Select the TCLK is an external input signal, A [3 .. 0] four separate buttons, selector all the way to the output with a different combination of buttons to choose from the four sub-frequency preferences and TCLK. Code is clear and easy to understand, does not meet the needs of your own expansion (2012-05-17, VHDL, 339KB, 下载12次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
The module' s function is to verify the implementation and the PC for basic serial communication functions. Installed on a PC requires a serial port debugging tool to verify the functionality of the program. Program implements a send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud law by the parameters defined in the program div_par decision to change the parameters of the corresponding baud rate can be achieved. The program is currently set div_par value 0x145, corresponding to the baud rate is 9600. 8 times the baud rate with a clock to send or receive every bit of the cycle time is divided into eight time slots so that the communication synchronization. (2011-06-22, VHDL, 349KB, 下载3次)
[VHDL/FPGA/Verilog] serial
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
程序的基本工作过程是，按动一个按键SW0，控制器向PC的串口发送“welcome"，
PC机接收后显示验证数据是否正确（串口调试工具设成按ASCII码接受方式）.
PC可随时向CPLD发送0-F的十六进制数据，CPLD接受后显示在7段数码管上.
The module s function is to verify the implementation and the basic PC, the serial communication function. Need PC,
Install a serial debugging tools to verify the functionality of the program.
Program implements a receive a 10 bit (ie no parity bit) of the serial controllers, 10
bit is a start bit, 8 data bits, 1 stop bit.
Serial Porter law defined by the program parameters div_par decision can change the parameters of the corresponding
Baud rate. Program the value of the current set div_par
Is 0x104, the corresponding baud rate is 9600. 8 times the baud rate with a clock will be sent or received per
A bit of the cycle time is divided into eight time slots in order to pass
Information synchronization.
The basic process is the work program, press a button SW0, the controller s serial port to the PC
"Welcome",
PC, after receiving the authentication data displayed is correct (serial debugging tool ASCII code set by the r (2010-11-28, VHDL, 2KB, 下载10次)
[VHDL/FPGA/Verilog] daima
寄存器组
1. 实验目的
(1)了解通用寄存器组的用途及对CPU的重要性。
(2)掌握通用寄存器组的设计方法。
2. 实验要求
设计一个通用寄存器组，满足以下要求：
(1)通用寄存器组中有4个16位的寄存器。
(2)当复位信号reset=0时，将通用寄存器组中的4个寄存器清零。
(3)通用寄存器组中有1个写入端口，当DRWr=1时，在时钟clk的上升沿将数据总线上的数据写入DR[1..0]指定的寄存器。
(4)通用寄存器组中有两个读出端口，由控制信IDC控制，分别对应算术逻辑单元的A口和B口。IDC=0选择目的操作数；IDC=1选择源操作数。
(5)设计要求层次设计。底层的设计实体有3个：通用寄存器组数据输入模块包括4个16位寄存器，具有复位功能和允许写功能；一个4选1多路开关，负责选择寄存器的读出。一个2路数据分配器实现数据双端口输出，顶层设计构成一个完整的通用寄存器组。
mhyjbn (2010-11-21, VHDL, 1KB, 下载26次)
[VHDL/FPGA/Verilog] DMX512_2_23
本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡，它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件，可以控制电脑灯或者其他DMX512协议的设备，比如LED灯、激光灯、PAR灯、DJ设备等等。
本系统还有体积小巧携带方便等特点，足够一般的娱乐场所、多功能厅、会议厅等场所使用，同时采用电脑进行灯光的控制，也可以提升工程的技术含量，显得更高科技。通过简单更改DMX模块的UART部分，还可以将串口转换usb接口，不过由于手头上的FPGA开发板没有USB接口，所以使用UART接口进行测试。
The system design using FPGA, a serial port on the computer then a DMX512 protocol adapter, it can make your computer into a super computer console or lighting console lights, LED controller. Through computer software, can control lights or other DMX512 protocol computer equipment, such as LED lights, laser lights, PAR lamps, DJ equipment. The system also features compact, portable and so on, is sufficient for most of the entertainment, function rooms, conference rooms and other places to use, while using computer control of lighting can also enhance the project s technical content, appears to higher technology. DMX module by simply changing the UART portion can also convert usb serial interface, however, because the FPGA development board on hand no USB interface, so tests using the UART interface.
(2010-07-11, VHDL, 2171KB, 下载270次)
[VHDL/FPGA/Verilog] Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a
本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础
上，采用超高速集成电路硬件描述语言(VeryHighspeedxntegatedeireuitHardware
DescriptionLan即age，简称VHDL)在Altera公司 Quartusll7.0开发环境下设计并实现各个功能块，通过仿真来证明功能正确性。再次，用 Protel99SE进行印制电路板(Prinicircuitboard，简称PcB)设计，从原理图到封装，再到布局布线。焊接调试完毕后，将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbPs，调制中频10MHz。测试结果验证系统的正确性，实现了从数字基带到中频的可4一DQPSK调制解调系统
This study is the first 4 1 DQPsK modem modulation system, part of the basic principles and design of each module, focusing on shaping filter and a direct digital frequency synthesizer (DireetoigitalFrequeneySynihesis, referred to as DDS), and to address all the key modules algorithm matlab design simulation to show simulation results. Second, the study of modulation and demodulation system demodulation part of the basic principles and design of each module, focusing on differential demodulation, digital down conversion and bit synchronization algorithm, but also for its various key module of the Matlab algorithm design and simulation. Then use the Matlab simulation of the entire system theory, reach a conclusion. On this basis,
, Using ultra-high speed integrated circuit hardware description language (VeryHighspeedxntegatedeireuitHardware
DescriptionLan that age, referred to as VHDL) in the Altera Corporation Quartusll7.0 development environment to design and implement the variou (2010-02-03, VHDL, 5330KB, 下载94次)
[VHDL/FPGA/Verilog] vhdl
《VHDL程序设计教程》光盘使用说明
本光盘是邢建平和曾繁太所著《VHDL程序设计教程》一书的配书光盘。本光盘的著作权归作者所有。
清华大学出版社享有该光盘的中文简体版专有出版权。
本光盘包括如下目录：
“e_teaching_vhdl”--CAI教学材料
包含全套的PowerPoint文件，可以直接用于教学，具体请参见该目录中的index.pps文件说明。
共包含前言、第一章到第六章的教学文件。目前包含的为中文版辅助材料。最新版本将在下面给出
的“www.its.sdu.edu.cn”网站不定期更新。
“vhdl fortextboot”--教程代码
包含本书教程例子的所有代码。
“vhdl for lab”--教程实验部分代码
包含本书教程实验部分所有代码。
“vhdl solutions”--教程习题参考解答
包含本书教程习题参考解答的文档。
“class music”--课间休息音乐欣赏
包含课间休息的中外音乐欣赏。
good (2009-10-08, VHDL, 2714KB, 下载8次)
[VHDL/FPGA/Verilog] myprojects
同步数字复接的设计及其FPGA实现
在简要介绍同步数字复接基本原理的基础上，采用VHDL语言对同步数字复接各组成模块进行了设计，并在ISE集成环境下进行了设计描述、综合、布局布线及时序仿真，取得了正确的设计结果，同时利用中小容量的FPGA实现了同步数字复接功能。
基群速率数字信号的合成设备和分接设备是电信网络中使用较多的关键设备，在数字程控交换机的用户模块、小灵通基站控制器和集团电话中都需要使用这种同步数字复接设备。近年来，随着需要自建内部通信系统的公司和企业不断增多，同步数字复接设备的使用需求也在增加。FPGA(现场可编程门阵列)器件的高性能简化了数字通信系统的设计与实现。本文基于FPGA的技术特点，结合数字复接技术的基本原理，实现了基群速率(2048kbps)数字信号的数字分接与复接。
VHDL (2009-04-30, VHDL, 2342KB, 下载95次)
[VHDL/FPGA/Verilog] shifter
移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。
CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。
SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions.
CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co (2009-04-26, VHDL, 126KB, 下载134次)
[VHDL/FPGA/Verilog] SPIsend
Verilog HDL的程式，上網找到SPI程式，
vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！
Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v! (2009-02-13, VHDL, 142KB, 下载61次)