DDR的控制器啦啦信不信由你非常实用又实用的历程哈
DDR MIG IT is my favorite pdf and FPGA projects yes you are right (2019-05-29, VHDL, 3214KB, 下载0次)
基2方法实现的8点fft，可以用于对fft的学习。
FFT 8 point implementation, the implementation of the base 2 algorithm, FPGA verification function. (2018-08-14, VHDL, 479KB, 下载0次)
ISCAS89测试基准电路，verilog编写，可用于测试向量的生成
iscas89 benchmark, written in verilog language, can be used to generate test pattern (2018-08-13, VHDL, 1010KB, 下载5次)
经典模式流水灯实验，拨码开关SW3作为开关信
号，导航按键UP和DOWN作为LED流动方向控制信
号，实现8个LED开关、方向可控的流水灯功能。
Classic mode flow lamp experiment, dial the code switch SW3 as a switch letter
Number, navigation buttons UP and DOWN as the LED flow direction control letter
8, to achieve the LED switch, the direction of the water lamp function. (2016-04-19, VHDL, 250KB, 下载1次)
arm9 的内核硬件描述语言,描述整个ARM系统的好的源代码
the descriptive language of the arm9，which completely describe a arm core. (2014-12-25, VHDL, 13KB, 下载4次)
分类中没有verilog，其实代码是verilog写的，大家下载的时候注意一下哈
There is no Verilog subcatalog in the list,so I choose the VHDL.Please pay attention to this when download it. (2013-07-25, VHDL, 2372KB, 下载1次)
对于初学者来说，FPGA的VGA显示，非常的基础，本文就介绍了，其基本用法。
For starters, the FPGA' s VGA display, the very basis of this paper, the basic usage. (2013-03-21, VHDL, 77KB, 下载3次)
synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。
synopsis sv training lab (2013-03-13, VHDL, 70KB, 下载70次)
模拟电路的基本教材，教会很多模拟电路的基本用法。
Basic textbook of analog circuits, basic usage of the Church of many analog circuits. (2012-12-04, VHDL, 1934KB, 下载4次)
Altera的高速收发器的ppt讲解，更好理解高速收发器
Altera' s high-speed transceiver ppt to explain, a better understanding of the high-speed transceiver (2012-08-24, VHDL, 774KB, 下载14次)
AMBA 源代码 包括仲裁模块，译码模块等。也包含了测试文件。
AMBA source code, including the arbitration module, decoding module. Also includes a test file. (2011-08-24, VHDL, 35KB, 下载17次)
本程序实现3*3中值滤波的Verilog语言编写
This procedure achieved 3* 3 median filter Verilog language (2011-08-24, VHDL, 52KB, 下载22次)
数字verilog设计数字算法CORDIC可以很好的为学生提供指导
Digital verilog design can be a good number of CORDIC algorithm to provide guidance for students (2011-05-13, VHDL, 5KB, 下载8次)
nor flash 控制器 硬件描述语言描述
nor flash controler (2011-05-09, VHDL, 367KB, 下载139次)
基于FPGA的TFT液晶驱动控制器设计源代码
FPGA-based TFT LCD driver controller source code (2011-04-09, VHDL, 851KB, 下载59次)
用于SD卡通信控制部分的数据收发部分，verilog语言描述
SD cards for some of the data send and receive communication control part, verilog language to describe the (2009-12-08, VHDL, 9KB, 下载8次)
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
(2009-04-27, VHDL, 4KB, 下载11次)
CLK 为其时钟脉冲
M 控制工作模式
CO 为允许带进位移位输入
S 控制移位模式0-3
D[7..0]是移位数据输入
QB[7..0]是移位数据输出
CN是移位数据输出进位
M for the clock pulse CLK mode control allow CO to enter into the S displacement control mode shift 0-3 D [7 .. 0] is the data input shift QB [7 .. 0] is the data output shift CN is a binary data output shift (2009-04-26, VHDL, 1408KB, 下载24次)
很好的状态机设计教程，尤其对于不同状态机的理解很好
Good state machine design tutorials, especially for the understanding of the different state machines very good (2008-05-19, VHDL, 949KB, 下载14次)