华为海思代码规则，华为海思代码应用规范，华为海思代码规范；
HUAWEI Hass code rules (2017-06-08, VHDL, 575KB, 下载49次)
计算机组成原理实验代码：单周期Cpu设计，附上检测指令， 在ISE 14.4通过检测
Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4 (2016-05-18, VHDL, 2270KB, 下载5次)
Xilinx 卷积码译码器IP核v6.2中文翻译，可作为快速入手译码器资料。
Xilinx convolutional code decoder IP core v6.2 Chinese translation, as fast start decoder available. (2015-12-30, VHDL, 99KB, 下载37次)
根据小波去噪的原理及特点，提出了用FPGA实现小波实时信号处理的方法。实验结果证明采用FPGA实现小波信号处理能在低信噪比的情况下有效去除噪声，同时能够满足信号处理系统的实时性要求。
According to the principles and characteristics of wavelet denoising, a method using wavelet FPGA real-time signal processing. Experimental results show that using FPGA wavelet signal processing at low signal to noise ratio can effectively remove noise while being able to meet the requirements of real-time signal processing system. (2015-02-28, VHDL, 503KB, 下载29次)
新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现
The new 32 booth multiplier implementations (2015-01-18, VHDL, 676KB, 下载27次)
一款低功耗HDMI信号输入，RGB信号输出，可以实现HDMI和DVI转RGB信号
A low-power HDMI signal input, RGB signal output can be achieved HDMI and DVI to RGB signals (2014-03-06, VHDL, 429KB, 下载19次)
由verilog编写的采用booth2编码的16*16乘法器
a 16*16 multiplier with booth2 coding by verilog (2013-08-04, VHDL, 13KB, 下载26次)
语音信箱控制模拟语音信箱收信、发信、存信、擦除信息等，允许用户发送信息、重阅信息、存储信息和擦除信息
Voicemail controlled analog voice mail reception, letter, Cunxin, erase information, allowing users to send messages, re-read the information, store information and erase information (2013-07-12, VHDL, 3KB, 下载2次)
PS2键盘和鼠标的显示实验的代码，浙江大学信电系高级数字系统实验的正确代码
PS2 keyboard and mouse showed that the experimental code, Zhejiang University, Department of Information and Electrical experiments of advanced digital systems correct code (2013-03-20, VHDL, 3KB, 下载9次)
this is the license genarator for xilinx ISE DESIGN SUIT 13.1
this is the license genarator for xilinx ISE DESIGN SUIT 13.1 (2011-10-04, VHDL, 286KB, 下载92次)
fpga工程师面试集锦，包含多家企业的面试题目，值得了解。
fpga engineer interview highlights, including a number of enterprises subject of the interview, it is worth understanding. (2011-05-11, VHDL, 105KB, 下载8次)
altera de2中文手册:de2提供了实用altera cyclone 2开发高级数字产品需要的所有模块.此为对应用户指南,在30分钟里面,可以浏览许多参考设计.
de2 user manual (2010-10-17, VHDL, 5045KB, 下载84次)
LAPS协议：系统启动后，LAPS协议处理器发送端处于空闲状态，此时它可以向理想信元发送数据允许信号TENB。理想信源收到TENB有效信号，就开始发送数据，它发送的是长度在4－1544字节之间变化的数据包，在数据包的第一字节发送同时，送出数据包开始指示TSOP，在数据包的最后一个字节，发送数据包结束指示TEOP。在数据包的发送过程中，LAPS协议处理器可以随时通过TENB通知理想信源暂停数据发送，直到TENB有效，再继续发送。
LAPS protocol: the system starts, LAPS protocol processor, the transmitter is idle, then it can send data to the ideal cell to allow signal TENB. Ideal signal source receive TENB effective, they begin to send data, it sends the changes in length between 4-1544 bytes of data packets, the first byte in the packet sent at the same time, start sending data packets directed TSOP, In the last byte of the packet, send packet end instruction TEOP. In the process of sending packets, LAPS protocol processor can notice at any time by TENB the ideal source suspend sending data until TENB be effective, then continue to send. (2010-05-17, VHDL, 3KB, 下载69次)
接收到数据后，波特率时钟启动信 clk_bps的高电平为接收或者发送数据位的中间采样点
Received data, the baud rate clock to start the letter clk_bps to receive or send a high data bit in the middle sampling point (2009-11-08, VHDL, 4KB, 下载7次)
实现一个加/减8进制计数器。其中包括时钟输入、使能信号、加减控制信
号、复位信号、三位输入和一位进位位。
To achieve a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit. (2009-09-02, VHDL, 32KB, 下载24次)
verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。
verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence. (2009-07-29, VHDL, 10308KB, 下载383次)
quartusii8.0正式版破解器,正式版可到官网去下载。http://www.altera.com.cn/
quartusii8.0_crack (2009-02-03, VHDL, 15KB, 下载48次)
同步设计规范，华为作为国内通信电子龙头企业，对VHDL设计的同步规范性文件
Synchronous design specifications, Huawei as a domestic leading enterprises in the electronic communications of synchronous VHDL design normative documents (2008-10-09, VHDL, 290KB, 下载36次)
比较对大比合并、等增益合并、选择合并接收算法的性能，信源输出用16位Walsh码扩频
Compared to the majority merger, the combined gain and so on, select receiver algorithm combined the performance of source output with 16-bit Walsh code spread-spectrum (2008-05-26, VHDL, 2KB, 下载36次)
学习嵌入式必须的东西，能够让你学起来是事半功倍，信不信你自己下了
Embedded learning to be something that allows you to learn from them is much more effective, believe it or not you own a (2008-04-04, VHDL, 297KB, 下载9次)