[VHDL/FPGA/Verilog] etop.cn_Clock_Dividers_Made_Easy
讲是时钟分频的一篇论文 各种分频 奇数偶数分频 分数分频
A Paper on Clock Frequency Dividing Various Frequency Dividing Even Frequency Dividing Fractional Frequency Dividing (2019-05-08, Verilog, 88KB, 下载2次)
[VHDL/FPGA/Verilog] eetop.cn_cordic_sqrt
cordic 算法知道正弦和余弦值，求反正切，即角度。
The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle. (2018-06-29, Verilog, 1KB, 下载7次)
[VHDL/FPGA/Verilog] fpgas_for_dummies_ebook_cn
因特尔所提供的fpga入门简单教程，面向外行人进行简单介绍。
Intel FPGA provided a simple entry tutorial, simple introduction for the layman. (2017-10-23, Verilog, 2291KB, 下载8次)
[VHDL/FPGA/Verilog] eetop.cn_数字IC面试题__8.3整理
数字ic面试题目以及一些面试的经验，帮助ic设计工作者找到人生中的第一份工作
Digital IC interview (2017-10-19, VHDL, 41KB, 下载12次)
[VHDL/FPGA/Verilog] Xilinx_convolution_coder_cn_v6.1
Xilinx的Convolution Encode v6.1手册的中文版，本人翻译。可作为快速学习卷积码编码资料。
The Xilinx Convolutional Encoder v6.1 manual Chinese version, my translation. Learn as fast convolution code information. (2015-12-30, VHDL, 161KB, 下载2次)
[VHDL/FPGA/Verilog] eetop.cn_double_fpu_latest[1].tar
浮点运算单元进行加减乘除运算，进行64位双精度浮点运算。
Floating-point arithmetic operations unit, double-precision 64-bit floating-point arithmetic (2014-05-29, VHDL, 364KB, 下载5次)
[VHDL/FPGA/Verilog] M-sequence-generator-
eetop.cn_Verilog编写的M序列发生器,//产生M序列的发送信号indata(随机),并且将接收到的解码信号（decode）进行比较。发送的头10个信号为1，第11个为0，在解码的开始时期进行同步判断时用到。
prepared by the M-sequence generator eetop.cn_Verilog / / M sequences generated transmission signal indata (random), and decodes the received signal (decode) for comparison. The first 10 to send a signal to the first 11 to 0, the decoding start time is used to synchronize the judgment. (2013-10-25, VHDL, 5KB, 下载18次)
[VHDL/FPGA/Verilog] eetop[1].cn_axibusregslice
axi总线读写通道插入一级寄存器模块verilog源码,已验证...
a slave interface is simple to achieve, need to look at (2013-04-10, VHDL, 2KB, 下载21次)
[VHDL/FPGA/Verilog] NIOS
nios那些事儿源码合集，一些常用的nios源码，建议新手，值得看信下
nios thing source collection, used nios source, it is recommended that novice, is worth the read the letter (2013-03-03, C/C++, 294KB, 下载37次)
[VHDL/FPGA/Verilog] top_8b_10b_code
光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信
号
光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信
号 (2011-11-30, VHDL, 1KB, 下载21次)
[VHDL/FPGA/Verilog] ee224
EE224 Sjsu exam material
EE224 Sjsu exam material (2011-03-04, VHDL, 9763KB, 下载1次)
[VHDL/FPGA/Verilog] dds-design
fpga实现dds，实现任意波形输出信，设计代码verilog
dds fpga realization (2010-12-21, Others, 1KB, 下载24次)
[VHDL/FPGA/Verilog] OneWireMaster
美信onewire总线IP core,带验证激励
MAXIM DS1WM
Synthesizable 1-Wire Bus Master IP core. (2010-12-10, VHDL, 55KB, 下载54次)
[VHDL/FPGA/Verilog] PM7832_IC-ON-LINE.CN
这个是分布式基站BBU和RRU的IR接口的接口芯片Datasheet
This is a distributed base station BBU and RRU' s IR interface interface chip Datasheet (2010-09-13, VHDL, 40KB, 下载8次)
[VHDL/FPGA/Verilog] vhdl
该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。
The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules. (2010-06-27, VHDL, 6KB, 下载46次)
[VHDL/FPGA/Verilog] CDC-Protocal(cn)
汽车音响CD机通讯控制协议CDC协议中文版。
CDC PROTOCAL (2010-06-04, Others, 235KB, 下载65次)
[VHDL/FPGA/Verilog] ML506_photo
XILINX ML506 开发板高清晰照片，用于学习virtex-5.
The photo of xilix ML506 board,there are high clear,using for learning VIETEX-5. (2009-12-11, Others, 3169KB, 下载42次)
[VHDL/FPGA/Verilog] cmd_pro
用于SD卡通信控制部分的命令收发部分，verilog语言描述
Communications control part for the SD card send and receive part of the command, verilog language to describe the (2009-12-08, VHDL, 7KB, 下载12次)
[VHDL/FPGA/Verilog] an499_CN
cpld 控制 8-32M sdram 控制器 maxII epm570实现。
pdf 的说明文件
CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation (2008-09-04, VHDL, 188KB, 下载94次)
[VHDL/FPGA/Verilog] up_261128143F5F01A9
为解决直接序列扩频系统的数字收发机中初始频率的捕获问题，提出了一种通过DFT变换，在频域
上进行抛物插值运算的频偏估计的算法。该算法可适应低信噪比、宽频率偏移范围的恶劣通信环境和突发的通信
模式，且算法复杂度较低。该算法已在FPGA 中实现。
To address the direct sequence spread spectrum system, the number of transceivers in the initial frequency of the capture problem, a transformation through the DFT, in the frequency domain for parabolic interpolation computing frequency offset estimation algorithms. The algorithm can be adapted to low signal to noise ratio, broadband rates offset the scope of bad communications environment and unexpected modes of communication, and the algorithm complexity low. The algorithm has been realized in the FPGA. (2007-12-01, Others, 62KB, 下载85次)