QNICE-FPGA是一个用于娱乐编程的16位计算机系统，作为一个成熟的片上系统端口...
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL. (2023-05-06, Assembly, 12587KB, 下载0次)
高等学校电子信息类专业系列教材 EDA原理及Verilog HDL实现 从晶体管、门电路到Xilinx Vivado的数字系统设计_14149516
EDA Principle and Verilog HDL realization from transistor, gate circuit to Xilinx Vivado digital system design _14149516 (2020-12-07, Others, 58789KB, 下载1次)
nand_flash的代码讲解，可能不是很详细，但是能够实现基本的功能，供大家进行参考教学
Nand_flash code explanation, may not be very detailed, but can achieve basic functions, for your reference (2020-03-28, Quartus II, 4KB, 下载3次)
本书的主要对象是IC设计工程师，帮助他们解决IC设计和综合过程中遇到的实际问题。
The main object of this book is IC design engineers, to help them solve the practical problems encountered in IC design and integration. (2019-12-18, Verilog, 5352KB, 下载6次)
Xilinx PCIE IP核的应用例程，带DMA，有V6和KC705的应用
Xilinx PCIE IP DMA example (2018-01-24, WINDOWS, 8385KB, 下载29次)
UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，
UVM entry example, a complete example of running through. These include the DUT code, the Testbench code, (2017-07-18, Verilog, 2966KB, 下载13次)
wolf 方法计算李雅普诺夫指数,实现用SDRAM运行nios，同时用SRAM保存摄像头数据，最大信噪比的独立分量分析算法。
wolf calculated Lyapunov exponent, Implemented with SDRAM run nios, while saving camera data SRAM, SNR largest independent component analysis algorithm. (2017-03-18, matlab, 4KB, 下载1次)
I2C slave功能模块的一种实现方式，简单易根据自己实际需求做修改，已经过FPGA验证可以很好的工作...
An implementation of I2C slave function modules, easy to make changes according to their actual needs, has been verified FPGA can work well ... (2016-07-10, Visual C++, 1KB, 下载1次)
计算机组成原理实验代码：单周期Cpu设计，附上检测指令， 在ISE 14.4通过检测
Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4 (2016-05-18, VHDL, 2270KB, 下载5次)
诚信商店0925企业版
后台地址:program/
用户/密码:master/master
you_mi/123456
Integrity Store 0925 Enterprise Edition
Background Address: program /
User/Password: master/master
you_mi/123456 (2016-03-09, C++ Builder, 4670KB, 下载1次)
Xilinx 卷积码译码器IP核v6.2中文翻译，可作为快速入手译码器资料。
Xilinx convolutional code decoder IP core v6.2 Chinese translation, as fast start decoder available. (2015-12-30, VHDL, 99KB, 下载37次)
新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现
The new 32 booth multiplier implementations (2015-01-18, VHDL, 676KB, 下载27次)
实现FPGA对SD卡数据的读取，采用fatfs形式读取，高效率
The FPGA to the SD card data read, read by fatfs, high efficiency
(2014-09-15, Unix_Linux, 82KB, 下载7次)
由verilog编写的采用booth2编码的16*16乘法器
a 16*16 multiplier with booth2 coding by verilog (2013-08-04, VHDL, 13KB, 下载26次)
PS2键盘和鼠标的显示实验的代码，浙江大学信电系高级数字系统实验的正确代码
PS2 keyboard and mouse showed that the experimental code, Zhejiang University, Department of Information and Electrical experiments of advanced digital systems correct code (2013-03-20, VHDL, 3KB, 下载9次)
PCIe体系结构导读，适合初次接触PCIe总线的人对PCIe整体结构的学习
The PCIe architecture REVIEW PCIe bus for the initial contact on the the PCIe overall structure learning (2012-08-31, PDF, 318KB, 下载136次)
应用MATLAB仿真8PSK调制解调以及其误码率与信噪比的关系
Using MATLAB simulation 8PSK modulation and demodulation, as well as the relationship between error rate and SNR
(2012-07-20, matlab, 3KB, 下载22次)
fpga工程师面试集锦，包含多家企业的面试题目，值得了解。
fpga engineer interview highlights, including a number of enterprises subject of the interview, it is worth understanding. (2011-05-11, VHDL, 105KB, 下载8次)
altera de2中文手册:de2提供了实用altera cyclone 2开发高级数字产品需要的所有模块.此为对应用户指南,在30分钟里面,可以浏览许多参考设计.
de2 user manual (2010-10-17, VHDL, 5045KB, 下载84次)
-- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
-- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
(2009-04-27, VHDL, 4KB, 下载71次)