乐曲硬件演奏电路的主系统由4个模块组成： FDIV、CODE_DATA、F_CODE和DRIVER。其中，模块U1（FDIV）是分频功能将输入的6MHz的时钟信号分频成1MHZ和4Hz的信号。U2（CODE_DATA）类似于弹琴的人的手指；模块U3（F_CODE）类似于琴键；模块U4（DRIVER）类似于琴弦或音调发声器。
The main system of musical performance circuit consists of 4 modules: FDIV, CODE_DATA, F_CODE and DRIVER. Wherein, the module U1 (FDIV) is a frequency division function to divide the input 6MHz clock signal into 1MHZ and 4Hz signals. U2 (CODE_DATA) resembles the fingers of a piano player; the module U3 (F_CODE) resembles a keyboard; the module U4 (DRIVER) is similar to a string or tone sounder. (2017-06-26, VHDL, 388KB, 下载2次)
基于FPGA的MT9M034图像采集显示并存在TF卡是的例程，FPGA和SDRAM完成了RAW图像的采集和转成RGB，并通过VGA显示。NIOS完成了RGB图像存成BMP图像的功能和CMOS的IIC配置
Based on FPGA MT9M034 image acquisition and displayed and TF card is routines, FPGA and SDRAM completed the acquisition of raw image and convert the RGB, and VGA display. NIOS completed the RGB image stored as a function of the BMP image and IIC CMOS configuration (2016-07-13, VHDL, 6726KB, 下载31次)
在DE2开发板上实现串口收发设计，系统时钟频率为50MHz,reset信号低电平有效，输入数据最高位为1时按位取反再输出
Achieve serial transceiver design DE2 board, the system clock frequency of 50MHz, reset active low signal, the input data is the most significant bit is 1. Bitwise re-export
Google 翻译（企业版）：译者工具包网站翻译器全球商机洞察
关于 Google 翻译社区移动Google 大全隐私权和使用条款帮助发送反馈 (2016-06-08, VHDL, 2KB, 下载5次)
用xilinx芯片实现千兆网的实例代码，您可以通过修改此代码完成基于ETMAC IP核的MAC设计，驱动外部PHY芯片或进行MAC to MAC 的直连通信设计。
this is code of etmac IP inst.. it will help you developing for MAC and PHY (2016-04-16, VHDL, 96KB, 下载105次)
小波变换是一种线性运算 , 它对信号进行不同尺度的分解 , 可有效地应用于如
信噪分离 , 提高时频两域的分辩率等 。本文讨论小波变换用于心电 Q RS 波形中细微特征
( 即高频成份特征 ) 提取的方法.
Wavelet transform is a linear operation, its signal is decomposed at different scales, can be effectively used as the signal to noise separation, the two time-frequency domain, such as to improve the resolution. This article discusses the wavelet transform of ECG waveform Q RS subtle features (ie, features high-frequency components) extraction method. (2015-02-28, VHDL, 145KB, 下载4次)
设 计与 实 现了 一种 以 F P GA 为核 心 的实 时 频 谱分 析 系 统。 系 统 包含 实时 频 谱 监 测 和 实 时 频 谱仪
2 种 频 谱分 析 模式 。 实 时频 谱 监 测 模 式采 用 F F T 算法 设 计实 现 , 用 于 对信 号 的 实时 监 测 实 时 频 谱 仪 模 式 采
用 D F T 算法 设计 实 现, 用于 信 号的 细致 分 析。 实验 证 明 , 系 统 充 分 利 用 了 F P GA 芯 片 的 资 源, 具 有 实 时 性好 、 频 谱
分析 参数 可 调、 多通 道循 环 切换 分析 等 特点 。目 前 该系 统已 成 功应 用于 HFC 双向 网 络反 向通 道 噪声 的 频谱 分 析 和 监
测之 中。
Design and Implementation of a kind FP GA as the core real-time spectrum analysis system. System includes real-time spectrum monitoring and real-time spectrum analyzer two kinds of spectrum analysis mode. Real-time spectrum monitoring mode using the FFT algorithm design and implementation for real-time monitoring of the signal real-time spectrum analyzer mode using DFT algorithm design and implementation, for a detailed analysis of the signal. Experimental results show that the system takes full advantage of FP GA chip resources, with real-time, spectral analysis parameters adjustable, multi-channel switching cycle analysis and so on. The spectral analysis of the current system has been successfully applied to a two-way HFC network and back-channel noise being monitored. (2015-02-28, VHDL, 213KB, 下载12次)
FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页
MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247 (2014-04-09, VHDL, 1690KB, 下载69次)
通过使用EDA工具，设计实现简易音乐播放器。在结合各个数字功能模块并利用FPGA系统本身丰富的物理资源的同时，将音乐的乐谱设计在FPGA内部，在Quartus II环境下，采用Verilog HDL 语言实现音乐合成器和播放系统。
By using EDA tools, design and implementation simple music player. The integration of the various functional modules and the use of FPGA digital system itself rich physical resources, will score the music inside the FPGA design, the Quartus II environment, using Verilog HDL language music synthesizer and playback system. (2013-06-13, VHDL, 4KB, 下载8次)
basys板描述介绍信号发生器在科研以及生产实践领域有着广泛的应用。传统的信号发生器通常是通过
模拟电路的振荡、变换得到各种信号。由于模拟器件以及模拟电路自身的局限性，其发展已
经遇到了瓶颈。直接数字
kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.This design can make adjustable sine,triangle and rectangle waveform.It also can show the waveform real time on a computer dispaly or a projecting apparatus via (2012-06-16, VHDL, 1221KB, 下载5次)
ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。
在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信）
ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from the control on the temperature, humidity, photoresistors, thermistors, and other information (including the main control machine from the control machine by zigbee protocol communications) (2012-05-18, VHDL, 1356KB, 下载23次)
dll for quartus ii 11.0 windows
dll for quartus ii 11.0 windows (2011-11-24, VHDL, 951KB, 下载205次)
采用全流水线结构，供初学者参考，附有仿真波形图，代码中上有可以改进之处，如蝶形单元中可以将4次乘法简化为3次乘法，不过要预先对旋转因子做处理，第一次上传，如有不妥之处，还请大家指正，谢谢。
With full pipeline structure, reference for beginners, with a simulation waveform diagram, the code can be on improvements, such as the butterfly unit can be reduced to 4 times 3 times multiplication multiplication, but to do pre-processing of the rotation factor, first upload, if inappropriate, but also please correct me, thank you. (2011-08-09, VHDL, 44KB, 下载11次)
使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快
Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language. Mixture of two languages can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon (2011-05-01, VHDL, 334KB, 下载6次)
用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。
Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data. (2010-09-09, VHDL, 36KB, 下载64次)
Altera FPGACPLD设计(高级篇)配套光盘,提供了书中所有示例的完整工程文件、设计源文件和说明文件。
每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。
Altera FPGACPLD Design (Advanced papers) supporting CD-ROM, the book provides a complete project files for all examples, the design source files and documentation. Each project includes examples of the project file, source documents, reports and other documents file and generate the results, the reader can use Quartus II or directly open the appropriate software. Design source file type according to the design input into the source code or schematic diagram, etc. (2010-08-30, VHDL, 54145KB, 下载190次)
用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或），crc解码，数据串行输出。
Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m sequence generated sparse 1, then the encoded data and XOR), crc decoding, serial output data. (2010-08-27, VHDL, 118KB, 下载30次)
首先介绍了LDPC码的校验矩阵和其因子表示方法，然后利用二分图对和积解码算法进行了详细的描述，最后给出了信度传播概率译码算法详细步骤，并对关键公式作了证明
This paper,first introduces the check matrix and the factor graph of LDPC,then describes the
sum-product algorithm by using the factor graph,and finally presents the detailed steps of the sum-product
algorithm and gives a proof of certain important expressions.
(2010-08-24, VHDL, 512KB, 下载42次)
在微型计算机系统中，CPU与外部的基本通信方式有两种，一种是并行通信即数据的各位同
时传送，其优点是传输速度较快，但数据有多少位就需要多少条传送线；而串行通信中数据一位一位顺序传
送，能节省传送线．用Vefilog HDL语言实现了串并、并串通信接口之间的转换
In the micro-computer systems, CPU basic communication with the outside there are two types of parallel data communication that you transmit at the same time, the advantage of faster transfer speeds, but the data how many how many transmission lines needed and the data in a serial communication send an order, to save transmission lines. With Vefilog HDL language to implement string and and the conversion between the serial communication interface (2010-05-27, VHDL, 159KB, 下载2次)
信號之值大部分跟狀態暫存器有關，所以當狀態暫存器改變一段時間後才能獲得，稱之為Ctrl_delay。另外指令解碼需要幾層之邏輯電路，因此延遲時間較長，稱為Dec_delay。
Most of the value of the signal with the state of the registers, when changing the state of registers after a certain period of time can be called Ctrl_delay. In addition the need for layers of instruction decode logic circuit, so the delay time is longer, as Dec_delay. (2009-07-10, VHDL, 170KB, 下载1次)
实时电话计费系统是企业、事业单位信息管理的一个重要组成部分。介绍了一种用FPGA 器件实现电话计费系统
的方法, 并给出了设计框图和详细设计过程, 设计采用Verilog_HDL 硬件语言。
Real-time telephone billing system is the enterprise information management institutions as an important component. Introduction of a FPGA device using telephone billing system methods, and gives the design diagram and detailed design process, design hardware Verilog_HDL language. (2008-07-11, VHDL, 519KB, 下载70次)