[VHDL/FPGA/Verilog] rmii-ethernet-mac
RMII接口以太网MAC核，用于10 100 MBit以太网实现，支持CDC和AXI Stream BUS，无管理，无...，
RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and without MDIO interface support (2022-01-21, VHDL, 0KB, 下载0次)
[VHDL/FPGA/Verilog] EthernetVideo
利用FPGA实现千兆以太网图像传输
Use FPGA to Transfer Image with Gigabits Ethernet (2020-12-02, VHDL, 28613KB, 下载0次)
[VHDL/FPGA/Verilog] vhdl-samples
包含基本数字电路的VHDL网表。
Contains VHDL netlists of basic digital circuits. (2019-03-09, VHDL, 1518KB, 下载0次)
[VHDL/FPGA/Verilog] eetop.cn_FFT(1)
基2方法实现的8点fft，可以用于对fft的学习。
FFT 8 point implementation, the implementation of the base 2 algorithm, FPGA verification function. (2018-08-14, VHDL, 479KB, 下载0次)
[VHDL/FPGA/Verilog] eetop.cn_ISCAS89(verilog)
ISCAS89测试基准电路，verilog编写，可用于测试向量的生成
iscas89 benchmark, written in verilog language, can be used to generate test pattern (2018-08-13, VHDL, 1010KB, 下载5次)
[VHDL/FPGA/Verilog] 以太网控制器Verilog源码(含有MAC,MII接口)
使用verilog语言完成MAC层代码的编写
Using the Verilog language to write the code of the MAC layer (2018-03-06, VHDL, 106KB, 下载18次)
[VHDL/FPGA/Verilog] eth_test_xps
基于xilinx SOC的SDK工程和最小系统ip核，可用于以太网测试，使用LWIP协议栈
The SDK works on xilinx SOC and minimum system ip nuclear, can be used for Ethernet testing, use LWIP Stack (2015-07-31, VHDL, 4021KB, 下载16次)
[VHDL/FPGA/Verilog] verilog_mac
该文档详细描述了以太网mac层的功能与实现，里面包括了verilog程序
The document describes in detail and implementation of Ethernet MAC layer functions, which includes the Verilog program
(2015-01-13, VHDL, 688KB, 下载8次)
[处理器开发] eetop.cn_arm9_compatiable_code_high
arm9 的内核硬件描述语言,描述整个ARM系统的好的源代码
the descriptive language of the arm9，which completely describe a arm core. (2014-12-25, VHDL, 13KB, 下载4次)
[其他嵌入式/单片机内容] eetop.cn_Solution-Manual
模拟电路的基本教材，教会很多模拟电路的基本用法。
Basic textbook of analog circuits, basic usage of the Church of many analog circuits. (2012-12-04, VHDL, 1934KB, 下载4次)
[VHDL/FPGA/Verilog] Libero_UG
libero的使用详细教程，比较详细，比官网上给的教程详细的多
libero use of detailed tutorials, a more detailed tutorial than the official website for more details (2011-05-01, VHDL, 12034KB, 下载49次)
[VHDL/FPGA/Verilog] stratixIII_3sl150_dev_TSE_SGMII_v1
该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。
因为altera官方没有这块板子的正确网卡与pc通信的程序，
Overall
This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit.
Designed by Quartus II/IP Cores/Nios II EDS v8.0
This is not an official released Design Example. It is only for your reference, but beyond the support area of ALTERA Mysupport.
(2010-12-22, VHDL, 7075KB, 下载36次)
[VHDL/FPGA/Verilog] SDC
quartus官网内总结的sdc有关资料学习
quartus official summary of the net to learn the information sdc (2010-07-22, VHDL, 825KB, 下载154次)
[VHDL/FPGA/Verilog] s3en_udp
基于spartan3e开发板嵌入式EDK开发的UDP协议网口开发程序
EDK embedded development board based on spartan3e UDP protocol developed network port development program (2010-05-13, VHDL, 18293KB, 下载71次)
[网络编程] AMBA
以太网技术入门的好资料，适合初学者和在职工程师
good (2009-08-26, VHDL, 867KB, 下载12次)
[VHDL/FPGA/Verilog] Register
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The termcnt (terminal count) output goes high when the register contains zero.
-- download from: www.fpga.com.cn & www.pld.com.cn
(2009-04-27, VHDL, 4KB, 下载11次)
[Windows编程] SDH
他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据
He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data (2009-03-26, VHDL, 6KB, 下载200次)
[VHDL/FPGA/Verilog] k21test
只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。
Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output. (2008-08-19, VHDL, 860KB, 下载47次)
[其他书籍] aybook.cn_veztjdsj1102
很好的状态机设计教程，尤其对于不同状态机的理解很好
Good state machine design tutorials, especially for the understanding of the different state machines very good (2008-05-19, VHDL, 949KB, 下载14次)
[单片机开发] ethernet.tar
10M/100M以太网ipcore，包括说明文档和整个源码
10M/100M Ethernet ipcore, including documentation and the source (2008-05-18, VHDL, 915KB, 下载222次)