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按平台查找All Verilog(155) 

[VHDL/FPGA/Verilog] Ethernet-verilog

以太网verilog
Ethernet verilog (2024-04-23, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1713832768229327.html

[博客] breaks

任天堂娱乐系统(NES)Famicom Famiclones芯片反转
Nintendo Entertainment System (NES) Famicom Famiclones chip reversing (2023-06-07, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1688509200423512.html

[电子书籍] fpgas-for-dummies-ebook-zh-cn.pdf

intel fpga dummies book
intel fpga dummies book (2020-06-17, Verilog, 2286KB, 下载0次)

http://www.pudn.com/Download/item/id/1592383778752724.html

[其他] eetop.cn_ddr4_verilog_models

which can be used in your testbench.
which can be used in your testbench. (2020-04-30, Verilog, 1065KB, 下载0次)

http://www.pudn.com/Download/item/id/1588237296727213.html

[VHDL/FPGA/Verilog] ethernet_mii_udp_1

Verilog开发的,MII接口的百兆以太网UDP代码
100 megabit Ethernet UDP code of MII interface (2020-03-20, Verilog, 3820KB, 下载26次)

http://www.pudn.com/Download/item/id/1584692361215646.html

[VHDL/FPGA/Verilog] Project_Gbit

pc与fpga之间通过千兆以太网交换机实现网络通信
Network communication between PC and FPGA via Gigabit Ethernet switch (2019-08-09, Verilog, 6734KB, 下载3次)

http://www.pudn.com/Download/item/id/1565364140626692.html

[硬件设计] xaui_crc

万兆以太网接口的crc校验程序,发送端添加crc,接收端校验crc并去掉crc。
CRC verification program for 10 Gigabit Ethernet interface (2019-06-19, Verilog, 18KB, 下载2次)

http://www.pudn.com/Download/item/id/1560910691809607.html

[VHDL/FPGA/Verilog] ethernet

实现100M到1G以太网通信,包括收发模块,PHY模块。
Realize 100M to 1G Ethernet communication, including transceiver module and PHY module. (2019-04-25, Verilog, 14266KB, 下载13次)

http://www.pudn.com/Download/item/id/1556157131110273.html

[其他] zip

use to matematical model folded convolution
use to matematical model folded convolution (2019-04-01, Verilog, 5KB, 下载0次)

http://www.pudn.com/Download/item/id/1554091229150042.html

[VHDL/FPGA/Verilog] src

以太网MAC数据链路层,在FPGA内用Verilog语言实现对应功能
Ethernet MAC layer,in FPGA, implement this function with verilog language (2018-08-07, Verilog, 60KB, 下载3次)

http://www.pudn.com/Download/item/id/1533656676295753.html

[VHDL/FPGA/Verilog] Chapter10 Sample

实现以太网功能,全部文件都包括,可以直接下载使用
Ethernet project file (2018-07-03, Verilog, 140KB, 下载2次)

http://www.pudn.com/Download/item/id/1530577591803720.html

[文章/文档] ISE_In-Depth_tutorial

官方教程,可以看看,是全英文的,请谅解,是官网下载分享,据说功能说明还要20个字,祝大家新年快乐,天天开心
The official tutorial, you can see, is all in English, please understand, is the official website to download and share, it is said that the function description is still 20 words, I wish you all a happy new year, happy every day (2018-07-01, Verilog, 3020KB, 下载0次)

http://www.pudn.com/Download/item/id/1530459259661480.html

[VHDL/FPGA/Verilog] ethernet_test

Verilog实现FPGA千兆以太网通讯,udp/ip协议,Wireshark抓包,亲测可用
Verilog implements FPGA Gigabit Ethernet communication, udp/ip protocol, Wireshark packet capture, pro test available. (2018-06-28, Verilog, 8055KB, 下载47次)

http://www.pudn.com/Download/item/id/1530172149546520.html

[VHDL/FPGA/Verilog] eetop.cn_spi.tar

基于wishbone总线的SPI主设备代码
spi master based on wishbone bus (2018-05-02, Verilog, 242KB, 下载2次)

http://www.pudn.com/Download/item/id/1525265751135515.html

[开源硬件] 7A50T

xilinx公司Artix7芯片。开发板全部资料包括以太网
Xilinx company Artix7 chip. All data of the development board include Ethernet (2018-03-16, Verilog, 59647KB, 下载31次)

http://www.pudn.com/Download/item/id/1521167925128651.html

[VHDL/FPGA/Verilog] Transmit_subsystem-master

千兆以太网的相关资料,包括相关的一些测试文件
Gigabit Ethernet related information (2018-03-16, Verilog, 2631KB, 下载1次)

http://www.pudn.com/Download/item/id/1521161229257703.html

[VHDL/FPGA/Verilog] ethernet_interface_20160424_A

基于Xilinx Spartan-6开发板,实现以太网通信
Ethernet communication (2018-02-26, Verilog, 24616KB, 下载7次)

http://www.pudn.com/Download/item/id/1519627345437333.html

[VHDL/FPGA/Verilog] ethernet_loopback

通过FPGA驱动千兆以太网口,完成SPARTAN6上的UDP数据包闭环测试,即通过网口发送数据包到FPGA,FPGA内部将接收到的数据返回到PC机,建议测试之前添加ARP静态绑定,FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到,发送端添加了CRC以及整体CHECKSUM的计算
Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation (2017-11-20, Verilog, 23381KB, 下载43次)

http://www.pudn.com/Download/item/id/1511144498493064.html

[VHDL/FPGA/Verilog] EGO1快速上手指南v1224

EGO1快速上手指南,适用于新手进行学习
EGO1 Quick Start Guide (2017-11-15, Verilog, 2980KB, 下载20次)

http://www.pudn.com/Download/item/id/1510722625810653.html

[VHDL/FPGA/Verilog] W5300_IF

实现FPGA与W5300 芯片的百兆以太网通信 ,实际项目中应用很多
Fast Ethernet communication between FPGA and W5300 chip, the actual project in many applications (2017-10-26, Verilog, 4KB, 下载102次)

http://www.pudn.com/Download/item/id/1508999227737035.html
总计:155