开发了两个FPGA之间的通信接口，该接口通过以太网通道发送数据，并采用arp、...
A communication interface between two FPGAs is developed which sends data through ethernet channel and employs arp, ethernet, ip and udp protocols and has a packet flow control mechanism. The hardware is described in Verilog and VHDL. (2017-12-26, VHDL, 73KB, 下载0次)
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Brand: New Era
Description
Exemplify your impressive Chicago Bulls fandom when you don this dynamic Draft 59FIFTY fitted hat from New Era. It'll be clear to everyone around you on game day that your enthusiastic Chicago Bulls fervor is nothing to be messed with when you sport this fresh cap! (2018-06-08, VHDL, 628KB, 下载1次)
opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。
Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim. (2016-05-03, VHDL, 994KB, 下载7次)
cycloneIV开发板完成图像数据采集，色彩空间转换，SDRAM存取数据，VGA控制等
CycloneIV development board to complete the image data acquisition, color space conversion, SDRAM access to data, VGA control etc (2015-02-02, VHDL, 23187KB, 下载13次)
CORTEX-M0处理器官方公开的源代码包！采用模糊网表生成，不可读但可综合可仿真可流片，还有testbench示例，很宝贵的资料！
CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable information! (2014-05-02, VHDL, 1201KB, 下载84次)
VHDL 实用教程
本书比较系统地介绍了VHDL 的基本语言现象和实用技术全书以实用和可操作为基点简洁而又不失完整地介绍了VHDL 基于EDA 技术的理论与实践方面的知识
VHDL practical tutorial book systematically introduces the basic phenomenon of VHDL language and practical skills book with practical and workable starting point is simple and yet complete introduction to the theory and practice of VHDL-based EDA technology knowledge (2013-12-09, VHDL, 2839KB, 下载2次)
altera DE2 开发板的重要应用接口，包括VGA，以太网通信，音频和视频解码，后续开发例程时可以直接使用其中的端口
altera DE2 development board important application interfaces, including VGA, Ethernet communications, audio and video decoding, the subsequent development of routines which can be used directly when the port (2013-08-20, VHDL, 37KB, 下载8次)
这个工程应用于千兆网传输的物理代码子层，同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。
This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36
and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
The differences between the 2 protocols are Link-timer and the control information exchanged during
Auto-negotiation process. (2013-08-08, VHDL, 16183KB, 下载89次)
这是黑金FPGA开发板关于verilog的例程代码，对于初学者是不错的入门资料
This is the black gold FPGA development board routines about verilog code for beginners is a good introductory information (2013-06-30, VHDL, 13024KB, 下载193次)
fpga与DSP通过emif接口通信，fpga内部通过fifo进行数据缓存
fpga with the DSP through emif interface communication, fpga internal data cache by fifo (2013-03-16, VHDL, 4KB, 下载41次)
这是用sopc搭建的一个工程，实现三速以太网的传输。开发版是3c120
This is an engineering sopc structures, triple-speed Ethernet transmission. The Developer Edition is 3c120 (2012-11-13, VHDL, 5217KB, 下载240次)
//奥科单片机网
//www.okmcu.net
//CPLD&FPGA实例
//奥科单片机助您成功
//本实验就是学习单个数码管的显示
//Bioko microcontroller network// www.okmcu.net// CPLD & FPGA instance// Bioko microcontroller to help you succeed// this experiment is to study a single digital tube display (2012-10-09, VHDL, 44KB, 下载3次)
该代码能实现基于DE-2开发板对88E1111网络接口的访问，是一个较好的代码例子。
The code achieves access 88E1111 internet interface based on DE-2，It is
a good example。 (2012-08-14, VHDL, 26197KB, 下载121次)
采用全流水线结构，供初学者参考，附有仿真波形图，代码中上有可以改进之处，如蝶形单元中可以将4次乘法简化为3次乘法，不过要预先对旋转因子做处理，第一次上传，如有不妥之处，还请大家指正，谢谢。
With full pipeline structure, reference for beginners, with a simulation waveform diagram, the code can be on improvements, such as the butterfly unit can be reduced to 4 times 3 times multiplication multiplication, but to do pre-processing of the rotation factor, first upload, if inappropriate, but also please correct me, thank you. (2011-08-09, VHDL, 44KB, 下载11次)
Xilinx公司推荐FPGA培
训教材Xilinx ISE 9.xFPGA/CPLD设计指南的配套光盘内容，每个程序含verilog和VHDL两具版本
Training materials recommended by Xilinx Xilinx ISE 9.xFPGA/CPLD FPGA design guidelines supporting the CD content, each program contains two versions of verilog and VHDL (2011-04-02, VHDL, 8569KB, 下载7次)
用xilinx公司的spartan-3e开发板实现一个视频采集的程序，采集进来的数据用LED代表显示出来。
Companies with xilinx spartan-3e development board to implement a video capture program, collecting on behalf of the incoming data with LED display (2011-03-21, VHDL, 3946KB, 下载6次)
FPGA实用程序，测试步进电机，开发环境为Quartus II 8.0 (32-Bit)，已经测试ok，供大家参考学习
FPGA utility, the test motor, development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning (2010-12-08, VHDL, 381KB, 下载35次)
适用于10GBase-T的以太网(802.3an协议)LDPC解码器, 用VHDL语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。
LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm (2010-03-10, VHDL, 864KB, 下载152次)
对camera_link接口传输过来的信号进行格式转换，将16bit并行转换成串行输出
Right camera_link interface transfer over the signal format conversion will be converted into serial 16bit parallel output (2009-10-15, VHDL, 1687KB, 下载141次)
TLC5510A是一款高速AD转换器，最高可以达到100MBPS，该程序以VHDL实现对TLC5510的控制
TLC5510A is a high-speed AD converter, the maximum can be achieved 100MBPS, the realization of the program to VHDL control of TLC5510 (2009-06-24, VHDL, 1438KB, 下载68次)