基于FPGA的MT9M034图像采集显示并存在TF卡是的例程，FPGA和SDRAM完成了RAW图像的采集和转成RGB，并通过VGA显示。NIOS完成了RGB图像存成BMP图像的功能和CMOS的IIC配置
Based on FPGA MT9M034 image acquisition and displayed and TF card is routines, FPGA and SDRAM completed the acquisition of raw image and convert the RGB, and VGA display. NIOS completed the RGB image stored as a function of the BMP image and IIC CMOS configuration (2016-07-13, VHDL, 6726KB, 下载31次)
基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫
Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-bit) FPGA using LCMXO2-1200HC-4MG132C clock 25M development board: EEFOUCS little Step (2016-06-28, VHDL, 199KB, 下载6次)
FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择
FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection (2015-11-18, VHDL, 168KB, 下载20次)
基 于 f p g a 的Marvell 88E1111 以 太 网 控 制 器 的 设 计，能发送接收，通过GMII接口实现TCP/UDP 传输
Base on fpga Marvell 88E1111 to mt net control device design, can send and receive, through GMII TCP/UDP transmission on the interface (2015-05-12, VHDL, 2238KB, 下载56次)
MPI接口就是CPU和逻辑之间通信的一个接口，一般使用总线方式，总线一般有两种标准，一种是MOTO模式，另外一种是intel模式。本资料包含verilog程序以及说明
MPI interface is an interface for communication between the CPU and logic, the general way of using the bus, the bus there are two standards, one is the MOTO mode, the other one is the intel mode. This information contains verilog procedures and instructions (2014-04-28, VHDL, 120KB, 下载6次)
通过使用EDA工具，设计实现简易音乐播放器。在结合各个数字功能模块并利用FPGA系统本身丰富的物理资源的同时，将音乐的乐谱设计在FPGA内部，在Quartus II环境下，采用Verilog HDL 语言实现音乐合成器和播放系统。
By using EDA tools, design and implementation simple music player. The integration of the various functional modules and the use of FPGA digital system itself rich physical resources, will score the music inside the FPGA design, the Quartus II environment, using Verilog HDL language music synthesizer and playback system. (2013-06-13, VHDL, 4KB, 下载8次)
88e1111的寄存器的控制，使用verilog，已经调试通过,能够对88e1111操作。
The 88E1111 register control, use verilog, and has been through debugging. (2012-07-07, VHDL, 1KB, 下载524次)
8B10B是应用最广泛的编码技术。它被用于串行连 接SCSI、串行ATA、光纤链路、吉比特以太网、XAUI（10吉比特接口）、PCIExpress总线、InfiniBand、 SeriaRapidIO、HyperTransport总线以及IEEE1394b接口（火线）技术中。
8b/10b has been widely adopted by a variety of high speed data communication standards
used today and should prove ever more useful for FPGA-based designs as clock speeds and
I/O capabilities increase.
8b/10b has been widely adopted by a variety of high speed data communication standards
used today and should prove ever more useful for FPGA-based designs as clock speeds and
I/O capabilities increase. (2012-05-22, VHDL, 3KB, 下载10次)
dll for quartus ii 11.0 windows
dll for quartus ii 11.0 windows (2011-11-24, VHDL, 951KB, 下载205次)
分析：制定规范
设计：状态图，真值表，编写代码。
验证：证明电路的正确性。仿真和形式化验
证。
综合：高层次到低层次转换。生成网表
测试：发现废品。生成测试向量
Analysis: norm design: state diagram, truth table, write the code. Authentication: proof of the correctness of the circuit. Simulation and formal verification. General: High level to low-level conversion. Netlisting test: find waste. Generate test vectors (2011-05-04, VHDL, 196KB, 下载3次)
使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快
Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language. Mixture of two languages can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon (2011-05-01, VHDL, 334KB, 下载6次)
提出一种适用于数字微波接力系统的基
带光纤拉远的接口方案 采用高性能千兆以太网物理层芯片 88E1111 和 1.25G 光收发器 SSFF3151 完成基带接口
基带信号可以通过数字光纤传输技术传到远端 并恢复射频信号 介绍了 88E1111 的工作原理 性能 接口等 并给出硬件电路设计的原理 以及各部分的具体实现方法和原理图
Compared with the traditional RF and IF pulls distant technology the baseband optical pulls distant technology
has some obvious superiority,especially in feeder line processing and choice of station site it has become the main pulls
distant technology in 3G network such as TD SCDMA.Refering to the baseband optical pulls distant technology in 3G
network the paper proposes a scheme which is suitable for the digital microwave relay system.The design uses high
performance Gigabit chip 88E1111 and 1.25G optical transceiver SSFF3151 to compelete the baseband interface.The signal
transmits to the remote through the digital fiber and restores the radio frequency signal.This paper introduces 88E1111 s
principle performance interface the hardware circuit design principles as well as part of the concrete implementation and
schematic diagrams.The scheme satisfies the baseband transmision in the stability and the error rate aspect.It can be used in
kinds of digital microwave relay systems. (2011-04-12, VHDL, 140KB, 下载137次)
介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；
AXI protocol described PPT, and a slave interface is simple to achieve, need to look at (2010-12-10, VHDL, 623KB, 下载461次)
Altera FPGACPLD设计(高级篇)配套光盘,提供了书中所有示例的完整工程文件、设计源文件和说明文件。
每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。
Altera FPGACPLD Design (Advanced papers) supporting CD-ROM, the book provides a complete project files for all examples, the design source files and documentation. Each project includes examples of the project file, source documents, reports and other documents file and generate the results, the reader can use Quartus II or directly open the appropriate software. Design source file type according to the design input into the source code or schematic diagram, etc. (2010-08-30, VHDL, 54145KB, 下载190次)
适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。
LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm (2010-03-10, VHDL, 606KB, 下载154次)
verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等
verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other (2009-12-19, VHDL, 12KB, 下载420次)
《VHDL程序设计教程》光盘使用说明
本光盘是邢建平和曾繁太所著《VHDL程序设计教程》一书的配书光盘。本光盘的著作权归作者所有。
清华大学出版社享有该光盘的中文简体版专有出版权。
本光盘包括如下目录：
“e_teaching_vhdl”--CAI教学材料
包含全套的PowerPoint文件，可以直接用于教学，具体请参见该目录中的index.pps文件说明。
共包含前言、第一章到第六章的教学文件。目前包含的为中文版辅助材料。最新版本将在下面给出
的“www.its.sdu.edu.cn”网站不定期更新。
“vhdl fortextboot”--教程代码
包含本书教程例子的所有代码。
“vhdl for lab”--教程实验部分代码
包含本书教程实验部分所有代码。
“vhdl solutions”--教程习题参考解答
包含本书教程习题参考解答的文档。
“class music”--课间休息音乐欣赏
包含课间休息的中外音乐欣赏。
good (2009-10-08, VHDL, 2714KB, 下载8次)
本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。
This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform. (2009-03-25, VHDL, 271KB, 下载33次)
链路铜梁调整机制的实现方案，该方案是在MSTP中实现链路容量动态调整的关键技术。是基于SDH中的VCAT，在未来的传送网通信中应用广泛
Link Tongliang realize adjustment mechanism program, which is in MSTP in the link capacity is dynamically adjusted to achieve the key technology. Is based on the SDH in the VCAT, the transmission network in the next letter, a wide range of applications (2008-07-12, VHDL, 13KB, 下载32次)
EPM1270和单片机的8080通讯接口，适合单片机与CPLD之间的高速通讯，verilog语言，QuartusII环境
EPM1270 and 8080 MCU communication interface for MCU and CPLD high-speed communication between, verilog language, QuartusII environment (2008-04-05, VHDL, 472KB, 下载229次)