The source code of Verilog HDL数字系统设计与验证 ——以太网交换机案例分析
The source code of Verilog HDL digital system design and verification -- Ethernet switch case study (2023-12-06, Verilog, 0KB, 下载1次)
在没有处理器的情况下使用以太网FMC的示例设计（即基于状态机），
Example designs for using Ethernet FMC without a processor (ie. state machine based), (2023-10-26, Verilog, 0KB, 下载0次)
一种测试设计，旨在了解如何在小型FPGA设计中使用三模式以太网MAC。，
A test design to see how the Tri-mode Ethernet MAC can be used in a small FPGA design., (2023-09-07, Verilog, 0KB, 下载0次)
针对Terasic DE2-115和Marvell 88E1111 PHY的以太网中继器的SystemVerilog实现，
A SystemVerilog implementation of a Ethernet Repeater targeting a Terasic DE2-115 and Marvell 88E1111 PHY, (2023-04-29, Verilog, 0KB, 下载0次)
加法器-计数器-乘法器-除法器-CRC移位器verilog模型，具有RTL和门级网表，
adder counter multiplier divider CRC shifter verilog model, with RTL and gate level netlist, (2023-05-15, Verilog, 0KB, 下载0次)
一种用于3D IC设计的基于GPT-GNN的verilog网表划分器，
A GPT-GNN based verilog netlist partitioner for 3D IC design, (2022-11-14, Verilog, 0KB, 下载0次)
纳斯达克HFT FPGA项目低延迟以太网模块的RTL实现。，
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project., (2023-08-12, Verilog, 0KB, 下载0次)
ECE 385最终项目——基于MAX10 DE10 Lite FPGA和Nios II软处理器的以太网
ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor (2021-12-13, Verilog, 8778KB, 下载0次)
使用GHDL将NEORV32处理器转换为可合成的纯Verilog网表模块。
Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (2023-05-15, Verilog, 11KB, 下载0次)
一个16点基-4 FFT芯片，包括Verilog代码、网表和布局。集团项目。
A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project. (2020-05-16, Verilog, 44475KB, 下载0次)
通过RGMII协议驱动的PHY芯片完成千兆以太网收发，包括ARP响应
With RGMII driving PHY IC to finish the internet communication (2020-08-05, Verilog, 4253KB, 下载7次)
数电实验FPGA verilog代码，包括秒表、全加器、半加器等。
FPGA Verilog code for digital experiment (2020-04-29, Verilog, 8KB, 下载1次)
本书的主要对象是IC设计工程师，帮助他们解决IC设计和综合过程中遇到的实际问题。
The main object of this book is IC design engineers, to help them solve the practical problems encountered in IC design and integration. (2019-12-18, Verilog, 5352KB, 下载6次)
本书介绍基于FPGA实现数字信号处理的原理与方法，作为Xilinx公司相关课程的培训教材
The FPGA implementation of DSP principle & method. (2019-08-09, Verilog, 3789KB, 下载6次)
基于EDA实验箱实现空气净化器五大功能：
自动模式 手动模式 睡眠模式 定时模式及提醒更换滤网功能。
本程序计时部分存在问题 其他功能均可实现
Based on EDA experimental box, five functions of air purifier are realized: automatic mode, manual mode, sleep mode, timing mode and reminding function of changing filter screen.
Problems in the timing part of this program and other functions can be realized (2019-07-04, Verilog, 793KB, 下载0次)
IIC从机模型，可综合RTL代码，经过了流片测试，绝对可靠。
IIC slave module,which is register transmit level code and can be synthesis.This design is tested by taped out and is reliable. (2019-05-09, Verilog, 589KB, 下载8次)
经典的verilog语言实现ICMP协议的参考代码
Reference Code of ICMP Protocol Implemented by Classical Verilog Language (2019-03-19, Verilog, 979KB, 下载5次)
详细的网口协议芯片器件资料，是开发该器件的必备资料
Detailed device information is essential for the development of the device. (2018-12-27, Verilog, 694KB, 下载15次)
功能验证了 8211EG千兆网卡 联合XilinxFPGA 的网卡数据发送数据 可广播 可单播
The function verifies that the network card data of 8211EG gigabit and XilinxFPGA can be broadcast on a single broadcast (2017-10-23, Verilog, 6086KB, 下载2次)
UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，
UVM entry example, a complete example of running through. These include the DUT code, the Testbench code, (2017-07-18, Verilog, 2966KB, 下载13次)