创建了Qsys系统，包括Nios II、三速以太网IP核、SGDMA控制器和其他用于传输的硬件组件...，
Created Qsys system that includes Nios II, Triple-Speed Ethernet IP Core, SGDMA controller and other hardware components for transmit and receive operation. Two Phase-Locked Loop modules are added to the design to generate clocks with different frequencies to make the Triple-Speed Ethernet system (which implements the MAC function) work (2017-01-03, Verilog, 0KB, 下载0次)
使用FPGA同时捕获来自多个ADC的数据。通过以太网+UDP流式传输捕获的数据。已测试...
Capture data from multiple ADCs concurrently using an FPGA. Stream the captured data out over ethernet + UDP. Tested on the Spartan 6 XC6SLX9, Wiznet W5500, and MCP3002 ADC. (2016-12-10, Verilog, 14KB, 下载1次)
生成给定Verilog Quartus Mapping（VQM）网表中所有节点的逗号分隔值（CSV）文件及其...
generates a Comma-Separated Values (CSV) file of all nodes in a given Verilog Quartus Mapping (VQM) netlist and their respective fanouts, ordered by fanout (highest first) (2017-04-25, Verilog, 498KB, 下载0次)
“基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片
In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution (2021-03-21, Verilog, 9441KB, 下载1次)
在图像处理领域，光线是非常重要的前提。灯源最好是环形灯，就像那些网红给自己打光一样，环形灯光照均匀。
WS2812B-LED环形灯工作时序
In the field of image processing, light is a very important premise. The best light source is the ring lamp, just like those net red lights, the ring light is uniform.
Working sequence of ws2812b-led ring lamp (2021-01-23, Verilog, 345KB, 下载0次)
《开源软核处理器OpenRisc的SOPC设计》介绍基于源代码开放的OpenRisc1200（以下简称OR1200）软核处理器的SOPC设计方法。《开源软核处理器OpenRisc的SOPC设计》分为两部分，第一部分介绍OR1200软核处理器的架构和配置、Wishbone总线的标准及OR1200软核处理器软硬件开发环境的建立；第二部分以具体实例说明如何使用OR1200软核处理器完成嵌入式设计，其中包括：调试接口的实现、OR1200控制片内存储器和I／O、串口、SDRAM、外部总线、以太网、LCD及SRAM；另外还介绍如何在OR1200上运行嵌入式Linux，并针对第二部分给出部分源代码。
《开源软核处理器OpenRisc的SOPC设计》适合对SOPC或OR1200软核处理器感兴趣的初学者使用，也可作为嵌入式系统设计人员的自学用书，或作为相关专业研究生的教材和教师的教学参考书。
Open source processor design method based on openriscor1200. The SOPC design of open source soft core processor openrisc is divided into two parts. The first part introduces the architecture and configuration of or1200 soft core processor, wishbone bus standard and the establishment of software and hardware development environment of or1200 soft core processor. The second part describes how to use or1200 soft core processor to complete embedded design with specific examples, including the implementation of debugging interface and or1200 control In addition, it introduces how to run embedded Linux on or1200, and gives some source codes for the second part.
SOPC design of open source soft core processor openrisc is suitable for beginners who are interested in SOPC or or1200 soft core processor. It can also be used as a self-study book for embedded system designers, or as a teaching reference book for graduate students and teachers. (2020-10-27, Verilog, 11722KB, 下载3次)
AMBA(Advanced Microcontroller Bus Architecture)先进的微控制器总线架构是一个免费、开放的标准，用于SoC内部功能模块之间的互连和管理。对成功设计一个有大量控制器和外设的多核处理器有很大的帮助。AMBA标准是免费的，独立于平台可以在任何处理器架构上使用。AMBA的广泛使用使得其具有众多合作伙伴支持的强健的生态系统，为来自不同设计团队和厂商的IP组件之间提供兼容性和可扩展性的保障。
Advanced microcontroller bus architecture (AMBA) is a free and open standard for interconnection and management of functional modules in SOC. It is helpful to design a multi-core processor with lots of controllers and peripherals. The AMBA standard is free, platform independent and can be used on any processor architecture. The widespread use of AMBA enables it to have a robust ecosystem supported by many partners, which guarantees the compatibility and scalability of IP components from different design teams and vendors. (2020-08-29, Verilog, 1077KB, 下载1次)
5G DU与RU间采用 eCPRI协议，ecpri 规范的范围是通过基于数据包的前端传输网络 (如 ip 或以太网) 实现高效、灵活的无线电数据传输。ecpri 定义了一个协议层, 它为协议堆栈的上层提供各种--主要是用户平面数据的特定--服务。
eCPRI protocol used in 5G Du and Ru (2020-04-01, Verilog, 1506KB, 下载10次)
多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。
Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions. (2019-06-08, Verilog, 18KB, 下载3次)
可编程数字系统设计的基本流程
设计输入（原理图文件、硬件描述语言文件、网表输入文件、混合输入文件）项目处理（设计文件检查和编译、设计文件分析和综合、器件适配、设置设计约束）设计校验（生成功能网表、功能仿真、适配后的仿真文件、门级时序仿真）器件编程（生成器件编程文件、器件编程）
原理设计输入方式是利用软件提供的各种原理图库，采用画图的方式进行设计输入。这是一种最为简单和直观的输入方式。原理图输入方式的效率比较低，一般只用于小规模系统设计，或用于在顶层拼接各个已设计完成的电路子模块。
Basic Flow of Programmable Digital System Design
Design Input (schematic diagram file, hardware description language file, netlist input file, mixed input file) project processing (checking and compiling design documents, analysis and synthesis of design documents, device adaptation, setting design constraints) design verification (generating functional netlist, function simulation, adapted simulation files, gate-level timing simulation) device programming (generating component programming text) Programming of Components and Devices
Principle design input mode is to use various schematic library provided by the software to design input by drawing. This is the simplest and most intuitive way to input. The input mode of schematic diagram is inefficient. It is usually only used for small-scale system design or for splicing each completed circuit sub-module at the top level. (2018-12-24, Verilog, 6632KB, 下载1次)
实现SPI总线接口转I2S总线接口数据传输
achieve spi bus to I2s bus by verilog (2018-09-14, Verilog, 90KB, 下载4次)
mux四选一及译码器：MUX电路在数字集成电路被广泛使用，作为寄存器或者其他电路的输入选择控制。也是ASIC设计中的基本门电路之一。
MUX four selection one and decoder (2017-12-06, Verilog, 2KB, 下载2次)
A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口
A/D sample data buffer to fifo,and then read enable to ethernet. (2017-10-23, Verilog, 1KB, 下载21次)
一些对初学者比较实用的源码，ASK，PSK，FSK调制解调
Some of the more practical source code for beginners (2017-10-15, Verilog, 1251KB, 下载52次)
Altera公司出的三速以太网例程，工程编译完了可以用niosii直接生成simple_socket_server，希望有用。
Altera company out of the three speed Ethernet routines, engineering finished, you can directly generate simple_socket_server using NiosII, I hope useful. (2017-09-16, Verilog, 1133KB, 下载20次)