Digilent FPGA平台，用于在vivado中便捷修改管脚xdc约束文件。
也可以去digilent官网GitHub下载 digilent-xdc
Can be downloaded in Digilent GitHub.
digilent-xdc (2021-04-24, VHDL, 83KB, 下载0次)
webstorm可安装包，包含破解方式
webstorm install path (2019-06-14, VHDL, 9852KB, 下载0次)
基于米尔官网的z_turn_mini的扩展板的原理图
Schematic diagram of z_turn_mini expansion board based on Mill's official website (2019-04-08, VHDL, 44KB, 下载0次)
xilinx官网的示例，led_shift_count代码，使用tcl脚本进行编译
Xilinx official website example, led_shift_count code, using TCL script to compile (2018-11-22, VHDL, 1380KB, 下载0次)
xilinx，microblaze的spi ip核的datasheet。xilinx官网速度慢，分享给有需要的朋友。
xilinx, microblaze the spi ip core datasheet. xilinx Officer slow speed of network share to a friend in need. (2016-07-06, VHDL, 435KB, 下载4次)
官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。
Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design. (2016-06-29, VHDL, 23KB, 下载2次)
塞琳思的开发板 大家可以下载看看 启智燧石系列的小例子
塞琳思 development board you can download a small example of enlightening look at the series of flint (2015-07-01, VHDL, 165KB, 下载2次)
本代码是实现计算器的功能，用的是VHDL语言编写，全部实现过程都在这里面。
This code is to achieve the functions of the calculator, using the VHDL language, to achieve full process on the inside
(2015-01-05, VHDL, 828KB, 下载1次)
实现视频处理中的sobel算法,提取图像的特征，是目标物提取必须的步骤。
Sobel for video processing algorithms (2014-12-10, VHDL, 2267KB, 下载30次)
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure. (2014-12-06, VHDL, 693KB, 下载6次)
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现
enternet verilog fpga (2013-12-15, VHDL, 60KB, 下载25次)
FPGA BASELINE ENCODER (jpeg mpeg)
FPGA BASELINE ENCODER (jpeg mpeg) (2013-08-19, VHDL, 224KB, 下载14次)
DE2-70开发板实验例程 中文非官网资料
DE2-70 development board test routines Chinese non-official website information (2013-07-08, VHDL, 7025KB, 下载88次)
Alrera FPGA SOC Cyclone V 官网开发板调试记录
Alrera FPGA SOC Cyclone V official website development board debug log (2013-06-07, VHDL, 1085KB, 下载46次)
xilinx SP605 板卡，网口设计。echo设计，实现接收单字符并返回的功能，同时从串口显示输出内容,具体流程也可以参加xilinx官网有个xapp1026的范例
Xilinx SP605 board, network port design. echo design, implementation, receiving single character and returns the output from the serial port at the same time (2013-04-18, VHDL, 12098KB, 下载27次)
以太网控制器的FPGA实现,用Verilog语言编写!
Ethernet controller FPGA, Verilog language! (2012-11-14, VHDL, 139KB, 下载12次)
actel fpga fusion kit 使用的flashrom操作
actel fpga fusion kit operation using flashrom (2011-08-31, VHDL, 386KB, 下载31次)
8b10b编解码，aurora协议，遵照xilinx官网文档
8b10b encoder and decoder, aurora protocol (2011-06-28, VHDL, 3KB, 下载62次)
xilinx官网edk实验，lab2，用nexys 2 板实验源代码
xilinx edk official website experiments, lab2, with nexys 2 plate test source code (2011-05-11, VHDL, 5020KB, 下载9次)
MAXplusⅡ入门与提高.rar
一本很经典的入门书
我们老师推荐的
MAXplus Ⅱ entry and improving. Rar is a classic primer recommended by our teachers (2008-06-27, VHDL, 12339KB, 下载99次)