这个CPU是一个简化的专门为教学目的而设计的RISC_CPU。 在设计中我们不但关心 CPU 总体设计的合理性， 而且还使得构成这个RISC_CPU的每一个模块不仅是可仿真的也都可以综合成门级网表。因而从物理意义上说，这也是一个能真正通过具体电路结构而实现的CPU。为了能在这个虚拟的CPU上运行较为复杂的程序并进行仿真, 我们把寻址空间规定为8K（即13位地址线）字节。
This CPU is a simplified RISC_CPU specially designed for teaching purposes. In the design, we not only care about the rationality of the overall design of CPU, but also make every module of RISC_CPU not only simulated, but also integrated into a gate-level network table. Therefore, physically speaking, it is also a CPU that can be realized through specific circuit structure. In order to run more complex programs on this virtual CPU and simulate them, we set the addressing space as 8K bytes (that is, 13-bit address line). (2019-09-22, VHDL, 346KB, 下载0次)