百胜帝宝官网B2024.CN娱乐总汇下载搜索联合开发网

[VHDL/FPGA/Verilog] openPowerlink-FPGA

基于FPGA的MN和CN开发
FPGA based MN and CN development (2014-01-29, C, 6354KB, 下载0次)

http://www.pudn.com/Download/item/id/1390956474755962.html

[VHDL/FPGA/Verilog] pp4fpgas-cn-hls

pp4fpgas的HLS项目-<https:github.com xupsh pp4fpgas-cn>
pp4fpgas的HLS项目-<https:github.com xupsh pp4fpgas-cn> (2021-04-12, Jupyter Notebook, 41097KB, 下载0次)

http://www.pudn.com/Download/item/id/1618213328951839.html

[VHDL/FPGA/Verilog] Verilog-OJ

Verilog在线评委服务器|verilogoj.ustc.edu.cn
Online judge server for Verilog | verilogoj.ustc.edu.cn (2023-05-09, Vue, 1334KB, 下载0次)

http://www.pudn.com/Download/item/id/1683641895428354.html

[VHDL/FPGA/Verilog] digilent-xdc-master

Digilent FPGA平台，用于在vivado中便捷修改管脚xdc约束文件。也可以去digilent官网GitHub下载 digilent-xdc
Can be downloaded in Digilent GitHub. digilent-xdc (2021-04-24, VHDL, 83KB, 下载0次)

http://www.pudn.com/Download/item/id/1619234594209628.html

[VHDL/FPGA/Verilog] xapp1052

xilinx官网 xapp1052资料，用于AXI总线挂DMA，没有账号的可以这里下载了。
Xilinx official network xapp1052 data,For AXI bus hanging DMA. no account can be downloaded here. (2018-07-18, Verilog, 14045KB, 下载36次)

http://www.pudn.com/Download/item/id/1531883701439092.html

[VHDL/FPGA/Verilog] xapp1052

赛灵思官方pcie例程，官网下载需要注册登录，这边给大家另一个选择
Xilinx PCIe official routines, the official website to download the required registration login, here give you another choice (2018-03-01, Verilog, 2811KB, 下载7次)

http://www.pudn.com/Download/item/id/1519885585733885.html

[VHDL/FPGA/Verilog] N25Q064A13E_VG12

nand flash 仿真模型，官网下载，希望对大家有用
This software code and all associated documentation, comments or other information (collectively "Software") is provided "AS IS" without warranty of any kind. (2017-07-23, Verilog, 133KB, 下载13次)

http://www.pudn.com/Download/item/id/1500824662678484.html

[VHDL/FPGA/Verilog] axi_spi_ds742

xilinx，microblaze的spi ip核的datasheet。xilinx官网速度慢，分享给有需要的朋友。
xilinx, microblaze the spi ip core datasheet. xilinx Officer slow speed of network share to a friend in need. (2016-07-06, VHDL, 435KB, 下载4次)

http://www.pudn.com/Download/item/id/1467794323897722.html

[VHDL/FPGA/Verilog] mt46v16m16p_ddr

官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。
Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design. (2016-06-29, VHDL, 23KB, 下载2次)

http://www.pudn.com/Download/item/id/1467172060391848.html

[VHDL/FPGA/Verilog] ethernet_test

以太网FPGA通信,verilog代码，实现双向通信
Ethernet FPGA communication (2016-01-20, Others, 2135KB, 下载36次)

http://www.pudn.com/Download/item/id/1453276523708075.html

[VHDL/FPGA/Verilog] ds182_Kintex_7_Data_Sheet

Xilinx kintex 7 的详细文档，从官网下载，编号DS-182
Xilinx kintex detailed documentation 7 downloaded the official website, No. DS-182 (2015-04-09, PDF, 647KB, 下载6次)

http://www.pudn.com/Download/item/id/1428584590754015.html

[VHDL/FPGA/Verilog] 7-timer

本代码是实现计算器的功能，用的是VHDL语言编写，全部实现过程都在这里面。
This code is to achieve the functions of the calculator, using the VHDL language, to achieve full process on the inside (2015-01-05, VHDL, 828KB, 下载1次)

http://www.pudn.com/Download/item/id/1420469463159785.html

[VHDL/FPGA/Verilog] Middle_League_SimuroSot-Program

fira5v5 比赛专用软件，由于之前的官网无法提供下载，现在分享一份。
fira5v5 race-specific software, can not be due to a previous official website available for download, now share a copy. (2013-07-23, C/C++, 6555KB, 下载9次)

http://www.pudn.com/Download/item/id/2312079.html

[VHDL/FPGA/Verilog] DE2_70

DE2-70开发板实验例程中文非官网资料
DE2-70 development board test routines Chinese non-official website information (2013-07-08, VHDL, 7025KB, 下载88次)

http://www.pudn.com/Download/item/id/2299709.html

[VHDL/FPGA/Verilog] Alrera-FPGA-SOC-Cyclone-V

Alrera FPGA SOC Cyclone V 官网开发板调试记录
Alrera FPGA SOC Cyclone V official website development board debug log (2013-06-07, VHDL, 1085KB, 下载46次)

http://www.pudn.com/Download/item/id/2272631.html

[VHDL/FPGA/Verilog] internet_test

xilinx SP605 板卡，网口设计。echo设计，实现接收单字符并返回的功能，同时从串口显示输出内容,具体流程也可以参加xilinx官网有个xapp1026的范例
Xilinx SP605 board, network port design. echo design, implementation, receiving single character and returns the output from the serial port at the same time (2013-04-18, VHDL, 12098KB, 下载27次)

http://www.pudn.com/Download/item/id/2206915.html

[VHDL/FPGA/Verilog] 8b10b

8b10b编解码，aurora协议，遵照xilinx官网文档
8b10b encoder and decoder, aurora protocol (2011-06-28, VHDL, 3KB, 下载62次)

http://www.pudn.com/Download/item/id/1583776.html

[VHDL/FPGA/Verilog] IEEE SystemVerilog3.1a语言参考手册.cn

IEEE SystemVerilog3.1a语言参考手册.cn.chm
IEEE SystemVerilog3.1a语言参考手册.cn.chm (2010-12-11, CHM, 6521KB, 下载32次)

http://www.pudn.com/Download/item/id/1376341.html

[VHDL/FPGA/Verilog] MAXplus

MAXplusⅡ入门与提高.rar 一本很经典的入门书我们老师推荐的
MAXplus Ⅱ entry and improving. Rar is a classic primer recommended by our teachers (2008-06-27, VHDL, 12339KB, 下载99次)

http://www.pudn.com/Download/item/id/499564.html

[VHDL/FPGA/Verilog] mo0re_FSM

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn
-- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn (2006-08-19, MultiPlatform, 1KB, 下载8次)

http://www.pudn.com/Download/item/id/209954.html