人工网表生成器，
Artificial Netlist Generator, (2023-03-13, Verilog, 0KB, 下载0次)
一个有趣的32位PowerPC类Linux RISC CPU，用于FPGA娱乐目的，
A for-fun 32-bit PowerPC -like Linux-capable RISC CPU for FPGA entertainment purposes, (2022-08-21, Verilog, 0KB, 下载0次)
亿龙网FPGA-10G回购
Yilong s NetFPGA-10G Repo (2015-05-07, Verilog, 59954KB, 下载0次)
NESTang是一款用Sipeed Tang Nano 20K和Primer 20K板实现的FPGA任天堂娱乐系统
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Nano 20K and Primer 20K boards (2023-05-19, Verilog, 758KB, 下载0次)
以太网MAC 10 100 Mbps
Ethernet MAC 10 100 Mbps (2019-10-02, Verilog, 978KB, 下载0次)
基于spatan6 x16 平台的以太网收报程序 (2022-04-26, Verilog, 104KB, 下载0次)
http://www.pudn.com/Download/item/id/1650987480972703.html
生成.v文件的模拟网表,用于BIST的仿真
generate .v file's net list (2021-01-12, Verilog, 543KB, 下载0次)
以太网MAC的VHDL代码
提供给设计嵌入式系统外接以太网接口时使用
VHDL code of Ethernet MAC
It can be used in the design of embedded system external Ethernet interface (2021-01-11, Verilog, 31KB, 下载1次)
千兆以太网，GMII口，udp模式传输数据，fpga控制
Gigabit Ethernet, gmii port, UDP mode data transmission, FPGA control (2020-09-11, Verilog, 9KB, 下载5次)
基于xilinx FPGA SPARTAN-6开发板的以太网通信代码，以太网芯片RTL8211EG，开发平台ISE
Ethernet communication code based on Xilinx FPGA spartan-6 development board, Ethernet chip rtl8211eg, development platform ISE (2020-05-20, Verilog, 7403KB, 下载7次)
对新手学习SRIO接口通信，有一定的帮助。希望能够获得更多这方面的进展。
It is helpful for novices to learn SRIO communication (2018-12-05, Verilog, 1469KB, 下载13次)
以太网协议 TCP/IP/DHCP协议verilog实现
Ethernet IP/TCP/DHCP verilog source code (2018-08-23, Verilog, 149KB, 下载47次)
用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核
With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core (2018-02-08, Verilog, 18855KB, 下载53次)
千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输
ethernet communication sample with verilog,state machine (2018-01-03, Verilog, 6940KB, 下载2次)
spi 模块代码 RTL verilog
spi rtl code (2017-12-08, Verilog, 42KB, 下载4次)
用Verilog编写的带FOFI的UART model，比较好
FOFIUART model wrote by Verilog coding (2017-11-24, Verilog, 171KB, 下载5次)
Verilog编写的UART通信模块，比较清晰
UART model wrote by Verilog (2017-11-24, Verilog, 9KB, 下载9次)
通用的GPIO coding，Verilog编码
GPIO coding wrote by Verilog (2017-11-24, Verilog, 9KB, 下载4次)
mii mac tx and rx，以太网mii接口收发
mii mac tx and rx Ethernet mii interface (2017-09-25, Verilog, 5KB, 下载14次)
异步FIFO的Verilog程序及其测试程序
FPGA/Verilog FIFO_ASYN (2017-09-14, Verilog, 67KB, 下载5次)