冲突以太网MAC tinytapeout模块
Clash ethernet MAC tinytapeout module (2024-05-04, Verilog, 0KB, 下载0次)
USB以太网FPGA卡
USB-Ethernet FPGA card (2023-11-11, Verilog, 0KB, 下载0次)
在SystemVerilog中实现的简单以太网接收机，
Simple ethernet receiver implemented in SystemVerilog, (2023-10-05, Verilog, 0KB, 下载0次)
多流以太网带宽控制，
Multi-Stream Ethernet Bandwidth Control, (2020-01-14, Verilog, 0KB, 下载0次)
基本Verilog以太网核心和C驱动程序功能，
Basic Verilog Ethernet core and C driver functions, (2023-09-14, Verilog, 0KB, 下载0次)
牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)
符合IEEE 802.3的以太网MAC
An Ethernet MAC conforming to IEEE 802.3 (2017-05-13, Verilog, 6412KB, 下载0次)
FPGA 百兆以太网
FPGA 100 Gigabit Ethernet (2019-02-23, Verilog, 33932KB, 下载0次)
VHDL中的SDH电信网（E1）
SDH telecommunications network (E1) in VHDL (2016-03-31, Verilog, 835KB, 下载0次)
Verilog以太网交换机（第2层）
Verilog Ethernet Switch (layer 2) (2021-07-27, Verilog, 147KB, 下载0次)
千兆以太网UDP通信驱动程序
Gigabit Ethernet UDP communication driver (2019-07-26, Verilog, 25KB, 下载1次)
用于FPGA实现的Verilog以太网组件
Verilog Ethernet components for FPGA implementation (2023-05-02, Verilog, 2375KB, 下载0次)
emmc储存芯片中英文协议，crc源码，sd驱动源码
EMMC storage chip Chinese and English protocol, CRC source, SD driver source (2021-04-13, Verilog, 4103KB, 下载2次)
三态以太网MAC控制器，支持10M/100M/1000M三种速率，采用wishbone总线
Three state Ethernet MAC controller, supporting 10m / 100M / 1000m three rates, using wishbone bus (2020-12-12, Verilog, 1135KB, 下载1次)
使用Verilog编写的管理以太网PHY的MDIO接口的控制器，在小梅哥AC620、AC6102开发板上验证通过，可以成功设置PHY芯片的链接速度到指定的速率。
The controller for managing the MDIO interface of Ethernet PHY written by Verilog has been verified on the development boards ac620 and ac6102 of xiaomeige, and can successfully set the link speed of phy chip to the specified speed. (2020-03-12, Verilog, 3KB, 下载21次)
基于ADV7511/ADV7511W/ADV7513的视频发生器
Video generator based on adv7511 / adv7511w / adv7513 (2020-01-25, Verilog, 194KB, 下载5次)
基于Verilog编写的串口通信协议模块
Serial communication protocol module based on Verilog (2017-11-24, Verilog, 5433KB, 下载8次)
verilog 编写的i2c代码，很好，很清晰
i2c coding wrote by verilog (2017-11-24, Verilog, 290KB, 下载10次)
用FPGA 编写的双端口的RAM，可以实现读写，希望通过这个平台与各个大神交流，希望得到大神的批评指正。
Prepared by FPGA double port RAM, you can read and write, and I hope that through this platform to communicate with the great gods, hoping to get criticism of the great god. (2017-08-10, Verilog, 7227KB, 下载4次)
这是小梅哥的qsys学习第三课的内容，这些资料供大家学习交流之用。
Processor
nios2 Nios II 13.0
All Components
nios2 altera_nios2_qsys 13.0
sdram altera_avalon_new_sdram_controller 13.0.1
uart_0 altera_avalon_uart 13.0.1
pio_led altera_avalon_pio 13.0.1
pio_key altera_avalon_pio 13.0.1
ir_decode ir_decode 1.0
altpll_0 altpll 13.0 (2017-07-09, Verilog, 9873KB, 下载1次)