[VHDL/FPGA/Verilog] snestang
用于Tang Primer 25K FPGA的超级任天堂娱乐系统
Super Nintendo Entertainment System for Tang Primer 25K FPGA (2024-01-07, SystemVerilog, 0KB, 下载0次)
[VHDL/FPGA/Verilog] src
以太网MAC数据链路层，在FPGA内用Verilog语言实现对应功能
Ethernet MAC layer,in FPGA, implement this function with verilog language (2018-08-07, Verilog, 60KB, 下载3次)
[VHDL/FPGA/Verilog] ethernet_interface_20160424_A
基于Xilinx Spartan-6开发板，实现以太网通信
Ethernet communication (2018-02-26, Verilog, 24616KB, 下载7次)
[VHDL/FPGA/Verilog] cheap_ethernet_latest.tar
用fpga实现的以太网ip协议，能实现1000m的速度，实现简单！
ip vhdl (2014-07-08, VHDL, 505KB, 下载12次)
[VHDL/FPGA/Verilog] 7_lan
FPGA 网口通信驱动 采用寄存器操作 已经通过验证
FPGA driver for lan port，operating on rejisters，tested successfully (2014-05-10, C/C++, 6KB, 下载9次)
[VHDL/FPGA/Verilog] Tri-Eth
采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输
Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed (2014-03-06, VHDL, 4714KB, 下载155次)
[VHDL/FPGA/Verilog] FPGADM9000AVerilog
FPGA控制DM9000A进行以太网数据收发的Verilog实现
FPGA control DM9000A Ethernet data transceiver Verilog realize (2013-11-27, VHDL, 4102KB, 下载14次)
[VHDL/FPGA/Verilog] eth
用数字逻辑语言描述以太网，百兆以太网MAC和MII的verilog源码
With digital logic language to describe Ethernet (2013-09-24, VHDL, 121KB, 下载13次)
[VHDL/FPGA/Verilog] 10_100m_ethernet-fifo
本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。
The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion. (2012-07-10, Others, 476KB, 下载8次)
[VHDL/FPGA/Verilog] eetop.cn_16bits_multiplier
16位并行乘法器源代码，booth2编码，二进制树拓扑结构
16bits parallel multiplier source code
(2012-07-07, VHDL, 586KB, 下载17次)
[VHDL/FPGA/Verilog] DE2_NET
基于altera的DE2开发板的以太网设计成功例程
Successful routine altera DE2 board Ethernet design
(2012-04-24, VHDL, 1785KB, 下载47次)
[VHDL/FPGA/Verilog] verilog-mac
这是一个以太网的mac程序，verilog写的，可方正 可实现
this is a mac implementation using verilog，you can emulate it or implement it directly (2012-01-07, Windows_Unix, 125KB, 下载129次)
[VHDL/FPGA/Verilog] ethernet10-100M-IP-core
以太网10-100M IP核Verilog源码，可综合
Ethernet 10-100M IP core Verilog source code can be integrated (2011-07-08, VHDL, 723KB, 下载21次)
[VHDL/FPGA/Verilog] ispLEVER
eetop.cn_ispLEVER培训教程FPGA设计流程.rar
eetop.cn_ispLEVER培训教程FPGA设计流程.rar (2010-02-21, C++ Builder, 633KB, 下载12次)
[VHDL/FPGA/Verilog] FPGA-DM9000A
FPGA控制DM9000A进行以太网数据收发的Verilog实现
FPGA control DM9000A for Verilog realization of Ethernet data sent and received (2010-01-17, VHDL, 2596KB, 下载457次)
[VHDL/FPGA/Verilog] ethernet
以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档
Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents (2009-10-21, VHDL, 825KB, 下载230次)
[VHDL/FPGA/Verilog] FPGAcontrolDM9000AuseVerilog
verilog控制以太网发送程序的实现，用于控制以太网发送
verilog control program for sending Ethernet implementation, used to control the Ethernet to send (2009-08-30, VHDL, 4KB, 下载71次)
[VHDL/FPGA/Verilog] ethnet
利用ALTERA公司Cyclone II 2C35 fpga芯片，实现以太网通信。以太网芯片为DM9000A
ALTERA companies use Cyclone II 2C35 fpga chips, Ethernet communications. Ethernet chips DM9000A (2008-09-12, VHDL, 538KB, 下载237次)
[VHDL/FPGA/Verilog] ETHERNET
具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述
With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog description (2008-03-04, MultiPlatform, 68KB, 下载723次)
[VHDL/FPGA/Verilog] fifo_01
8位相等比较器，比较8位数是否相等
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
-- download from www.pld.com.cn & www.fpga.com.cn
eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn (2006-08-19, MultiPlatform, 1KB, 下载13次)