一个简单的AES加密，流程清晰。包括了五个步骤：密钥扩展、字节替换、行移位、列混淆以及轮密钥加，能后比较直观的进行了解。
A simple AES encryption, clear process. It consists of five steps: key expansion, byte replacement, row shift, column confusion and round key addition, which can be solved intuitively. (2018-12-11, C/C++, 2574KB, 下载0次)
曼彻斯特编码（Manchester Encoding），也叫做相位编码（ Phase Encode，简写PE），是一个同步时钟编码技术，被物理层使用来编码一个同步位流的时钟和数据。它在以太网媒介系统中的应用属于数据通信中的两种位同步方法里的自同步法（另一种是外同步法），即接收方利用包含有同步信号的特殊编码从信号自身提取同步信号来锁定自己的时钟脉冲频率，达到同步目的。
Manchester Encoding, also known as Phase Encode (PE), is a synchronous clock encoding technique used by the physical layer to encode the clock and data of a synchronous bit stream. Its application in the Ethernet media system belongs to the self-synchronization method in the two bit synchronization methods in data communication (the other is the external synchronization method), that is, the receiver extracts the synchronization from the signal itself by using the special code containing the synchronization signal. The signal is used to lock its own clock frequency for synchronization purposes. (2018-11-09, C/C++, 320KB, 下载0次)
VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。
VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 line -3 line priority encoder, 8 select 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital clock, sequence detector design, general state machine and so on. (2018-02-26, C/C++, 444KB, 下载1次)
VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。
VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc.. (2018-02-26, C/C++, 443KB, 下载1次)
板子通过USB加电后，先向串口1输出一串测试数据，然后USB被PC识
别出来，虚拟出一个串口号给这个USB设备，此时可以通过在PC端的串口助手类
软件选择该串口号。
The board is powered via USB they ask a bunch of test data output port 1, and then identified by PC USB, a virtual serial port number to the USB device, this time through the serial port on the PC side helper class software select the serial number. (2013-07-23, C/C++, 4383KB, 下载1次)
详细的介绍巴特沃斯滤波器的结构和原理，以及滤波器系数计算，滤波器的设计
Detailed introduction to the structure and principles of the Butterworth filter, and the filter coefficient calculating filter design (2012-12-17, C/C++, 517KB, 下载6次)
1、按键可以调整当时时间
2、按键可以调节定时时间
3、定时时间到继电器吸合
*8位数码管显示 时间格式格式 12-08-00 标示12点08分00秒
S1 用于小时 加1操作
S2 用于小时减1操作
S3 用于分钟 加1操作
S4 用于分钟减1操作
* 8 digital display time format format 12-08-00 labeled S1 is used to 12:08:00 hours plus, buttons can adjust the time two buttons can adjust the regular time, regular time to relay an operation S2 for hours minus one operation S3 for minutes plus 1 Operating S4 used for the minute decrement (2012-07-13, C/C++, 14KB, 下载3次)
指令寄存器：在触发时钟的正沿触发下，寄存器将数据总线送来的指令存入寄存器；
累加器用于存放当前的结果，它也是双目运算的一个数据来源；
算术逻辑运算单元根据输入的8种不同操作码实现相应的加、与、异或、或等8种基本操作运算；
状态控制器实际上就是一个状态机，它是CPU的控制核心，用于产生一系列的控制信号，启动或停止某些部件。CPU何时进行读指令、读写I/O端口、对ROM数据的读取等操作，都是由状态机来控制的；
Instruction Register: The trigger is edge triggered clock, the register will be sent to the instruction data bus into the register accumulator for storing the current results, it is also a source of data binary operator arithmetic logic operation unit 8 according to the input different realization of corresponding processing operation code, AND, XOR, or 8 kinds of basic operations such as computing state controller is actually a state machine, which is the control of CPU core, used to generate a series of control signals to start or to stop some of the components. CPU when the read instruction, read and write I/O ports, read the data on the ROM and other operations are controlled by the state machine (2011-02-22, C/C++, 24KB, 下载2次)
采用altera mac核加88e111物理层芯片的千兆网方案，该文件是配置mac层和物理层的nios文件，基于hello world small工程。
88e111 by altera mac core and Gigabit Ethernet physical layer chip of the program, the file is configured mac layer and physical layer nios file, based on hello world small projects. (2010-06-02, C/C++, 1KB, 下载137次)
128乘法模拟器
c
M位乘N位不带符号整数的阵列乘法中加法---移位操作的被加数矩阵.每一部分乘积项ab叫做一个被加数.m*n个被加数可以用m*n个”与门”并行的产生.
以5位乘5位不带符号的阵列乘法器(m=n=5)为例(如下图):
FA为一位全加器,FA的斜线方向为进位输出,竖线方向为和输出,而所有被加数项的排列和正常的A*B=P乘法过程中的被加数矩阵相同.图中用矩形围成的阵列中最后一行构成一个行波进位加法器,其时间延迟为(n-1)2T.当然,为了缩短加法时间,最后一行的行波进位加法器也可以用先行进位加法器来代替.这种乘法器实现n位×n位时,需要n(n-1)个全加器和n2个”与”门.
err (2007-03-18, C/C++, 46KB, 下载8次)
一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。
a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment. (2006-03-21, C/C++, 121KB, 下载27次)
减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d
a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d (2005-06-16, C/C++, 109KB, 下载26次)